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authorArne Georg Gleditsch <arne.gleditsch@numascale.com>2010-09-09 14:54:07 +0000
committerMyles Watson <mylesgw@gmail.com>2010-09-09 14:54:07 +0000
commitd6689ed7813b37c92bbe6058155d67c4757fef26 (patch)
tree2067aa432c89740cb808662de827a6d32970d1c3 /src/cpu
parente0a000cc12984700c87fea6b153fa4221a125e19 (diff)
downloadcoreboot-d6689ed7813b37c92bbe6058155d67c4757fef26.tar.xz
Please find appended. This patch gets rid of the %gs magic altogether,
fixes a few alignment wrinkles and sets up and registers the MMCONF area for AMD Fam10h CPUs (where selected by mainboard configuration). It removes a bit of code that proved troublesome in MMCONF setups from mcp55_early_setup_car.c, as per earlier discussion. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/model_10xxx/init_cpus.c30
1 files changed, 13 insertions, 17 deletions
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index b5947c9d33..bbaa4819b2 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -57,32 +57,28 @@ static void set_EnableCf8ExtCfg(void)
static void set_EnableCf8ExtCfg(void) { }
#endif
-/*[39:8] */
-#define PCI_MMIO_BASE 0xfe000000
-/* because we will use gs to store hi, so need to make sure lo can start
- from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/
+
+#define _ULLx(x) x ## ULL
+#define _ULL(x) _ULLx(x)
+
+/*[63:0] */
+#define PCI_MMIO_BASE _ULL(CONFIG_MMCONF_BASE_ADDRESS)
static void set_pci_mmio_conf_reg(void)
{
#if CONFIG_MMCONF_SUPPORT
+# if PCI_MMIO_BASE > 0xffffffff
+# error CONFIG_MMCONF_BASE_ADDRESS must currently fit in 32 bits!
+# endif
msr_t msr;
msr = rdmsr(0xc0010058);
msr.lo &= ~(0xfff00000 | (0xf << 2));
- // 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
- msr.lo |= ((8 + CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
+ // 256 buses, one segment. Total 256M address space.
+ msr.lo |= (PCI_MMIO_BASE & 0xfff00000) | (8 << 2) | (1 << 0);
msr.hi &= ~(0x0000ffff);
- msr.hi |= (PCI_MMIO_BASE >> (32 - 8));
- wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
-
- //mtrr for that range?
- // set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
-
- set_wrap32dis();
-
- msr.hi = (PCI_MMIO_BASE >> (32 - 8));
- msr.lo = 0;
- wrmsr(0xc0000101, msr); //GS_Base Reg
+ msr.hi |= (PCI_MMIO_BASE >> (32));
+ wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
#endif
}