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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-29 06:56:52 +0100
committerNico Huber <nico.h@gmx.de>2018-10-30 09:41:08 +0000
commitdfbe6bd5c38d5feb6aa2778b2351cb13e0b1ecc8 (patch)
treebb12699462930eb270314a1db317a454cd7ff4c6 /src/cpu
parentb06f8ddfe8c0e18f962f8b5507a40f4ef430ffc1 (diff)
downloadcoreboot-dfbe6bd5c38d5feb6aa2778b2351cb13e0b1ecc8.tar.xz
src: Add missing include <stdint.h>
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/model_206ax/model_206ax.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index f4d469c9cf..2bf9d32e46 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -17,6 +17,8 @@
#ifndef _CPU_INTEL_MODEL_206AX_H
#define _CPU_INTEL_MODEL_206AX_H
+#include <stdint.h>
+
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
#define SANDYBRIDGE_BCLK 100