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authorArne Georg Gleditsch <arne.gleditsch@numascale.com>2010-09-13 15:11:35 +0000
committerMyles Watson <mylesgw@gmail.com>2010-09-13 15:11:35 +0000
commite7a5b76a748a27b033122b55356661b79839874c (patch)
tree586b516fe026b39a719f1c54cd04c4ced0b00878 /src/cpu
parentd09d1f7846d546f1790cd9db107014ffec92cc27 (diff)
downloadcoreboot-e7a5b76a748a27b033122b55356661b79839874c.tar.xz
Move initialization of MMCONF BAR to cache_as_ram setup phase, in order
to make sure MMCONF is set up before use. Otherwise, PCI config accesses run before init_cpus() will be lost if MMCONF is enabled (unless explicitly done as port-based accesses). This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in mcp55_early_setup, so reinsert. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc16
-rw-r--r--src/cpu/amd/model_10xxx/init_cpus.c27
2 files changed, 15 insertions, 28 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index aedb2fd564..e21462a30b 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -27,6 +27,7 @@
/* for CAR with FAM10 */
#define CacheSizeAPStack 0x400 /* 1K */
+#define MSR_MCFG_BASE 0xC0010058
#define MSR_FAM10 0xC001102A
#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
@@ -115,7 +116,7 @@ CAR_FAM10_out:
/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
* Re-enable it in after RAM is initialized and before CAR is disabled
*/
- movl $0xc001102a, %ecx
+ movl $MSR_FAM10, %ecx
rdmsr
bts $15, %eax
wrmsr
@@ -136,6 +137,19 @@ CAR_FAM10_out:
/* Erratum 343 end */
+#if defined(CONFIG_MMCONF_SUPPORT)
+ /* Set MMIO Config space BAR */
+ movl $MSR_MCFG_BASE, %ecx
+ rdmsr
+
+ andl $(~(0xfff00000 | (0xf << 2))), %eax
+ orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000) | (8 << 2) | (1 << 0)), %eax
+ andl $(~(0x0000ffff)), %edx
+ orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx
+
+ wrmsr
+#endif
+
CAR_FAM10_out_post_errata:
/* Set MtrrFixDramModEn for clear fixed mtrr */
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index bbaa4819b2..ae1da66967 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -58,30 +58,6 @@ static void set_EnableCf8ExtCfg(void) { }
#endif
-#define _ULLx(x) x ## ULL
-#define _ULL(x) _ULLx(x)
-
-/*[63:0] */
-#define PCI_MMIO_BASE _ULL(CONFIG_MMCONF_BASE_ADDRESS)
-
-static void set_pci_mmio_conf_reg(void)
-{
-#if CONFIG_MMCONF_SUPPORT
-# if PCI_MMIO_BASE > 0xffffffff
-# error CONFIG_MMCONF_BASE_ADDRESS must currently fit in 32 bits!
-# endif
- msr_t msr;
- msr = rdmsr(0xc0010058);
- msr.lo &= ~(0xfff00000 | (0xf << 2));
- // 256 buses, one segment. Total 256M address space.
- msr.lo |= (PCI_MMIO_BASE & 0xfff00000) | (8 << 2) | (1 << 0);
- msr.hi &= ~(0x0000ffff);
- msr.hi |= (PCI_MMIO_BASE >> (32));
-
- wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
-#endif
-}
-
typedef void (*process_ap_t) (u32 apicid, void *gp);
//core_range = 0 : all cores
@@ -295,9 +271,6 @@ static u32 init_cpus(u32 cpu_init_detectedx)
* already set early mtrr in cache_as_ram.inc
*/
- /* enable access pci conf via mmio */
- set_pci_mmio_conf_reg();
-
/* that is from initial apicid, we need nodeid and coreid
later */
id = get_node_core_id_x();