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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 00:01:33 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-23 19:15:20 +0200 |
| commit | e9a9c6a33cfc066b690082e938d84b318f6de32a (patch) | |
| tree | 7a9735b6998594ce52277be5699a5cbdb0e4104a /src/cpu | |
| parent | 3f22abb0a7260d0bdbffff6b1f459be6c55d042f (diff) | |
| download | coreboot-e9a9c6a33cfc066b690082e938d84b318f6de32a.tar.xz | |
intel/haswell: Remove useless MTRR clear
At this state, variable MTRRs are disabled. We overwrite this MTRR entry
before they are re-enabled.
Change-Id: Ieedf90f65514d848905626e75be496e08f710d91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15794
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index fe595fbd22..9cdb176ea4 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -209,14 +209,6 @@ before_romstage: andl $~1, %eax wrmsr - /* Clear MTRR that was used to cache MRC */ - xorl %eax, %eax - xorl %edx, %edx - movl $MTRR_PHYS_BASE(2), %ecx - wrmsr - movl $MTRR_PHYS_MASK(2), %ecx - wrmsr - post_code(0x33) /* Enable cache. */ |