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authorStefan Reinauer <stepan@openbios.org>2005-12-01 11:01:01 +0000
committerStefan Reinauer <stepan@openbios.org>2005-12-01 11:01:01 +0000
commitf5183cfa19ea4d235ac9e1206c8510c8c83ace0e (patch)
treea5d408e2f57eeea14a64edab0a25de587e9835aa /src/cpu
parent806e146e754a44f96c693cde707065b14f80d8a2 (diff)
downloadcoreboot-f5183cfa19ea4d235ac9e1206c8510c8c83ace0e.tar.xz
Applying YhLu's patch from issue 37.
a. apic id liftting to way that kernel like and let bsp to stay with 0 b. hw memhole: solve if hole_startk == some node basek This, together with the previous one will break most of the tree, but Yinghai Lu is really good at fixing things, so... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/dualcore/amd_sibling.c187
-rw-r--r--src/cpu/amd/dualcore/dualcore_id.c2
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_init.c134
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_msr.h21
4 files changed, 188 insertions, 156 deletions
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index a8b3592b5f..f961f50b2c 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -1,5 +1,4 @@
/* 2004.12 yhlu add dual core support */
-/* 24 June 2005 Cleaned up dual core support Eric Biederman */
#include <console/console.h>
#include <cpu/cpu.h>
@@ -10,100 +9,13 @@
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <cpu/x86/mtrr.h>
-#include "../model_fxx/model_fxx_msr.h"
-#include "../../../northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_msr.h>
+#include <cpu/amd/model_fxx_rev.h>
static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
-void amd_sibling_init(device_t cpu, struct node_core_id id)
-{
- unsigned long i;
- unsigned siblings, max_siblings;
-
- /* On the bootstrap processor see if I want sibling cpus enabled */
- if (first_time) {
- first_time = 0;
- get_option(&disable_siblings, "dual_core");
- }
-
- siblings = cpuid_ecx(0x80000008) & 0xff;
- printk_debug("%d Sibling Cores found\n", siblings);
-
- /* For now assume all cpus have the same number of siblings */
- max_siblings = siblings + 1;
-
- /* Wishlist? make dual cores look like hyperthreading */
-
- /* See if I am a sibling cpu */
- if (disable_siblings && (id.coreid != 0)) {
- cpu->enabled = 0;
- }
-
- if (id.coreid == 0) {
- /* On the primary cpu find the siblings */
- for (i = 1; i <= siblings; i++) {
- struct device_path cpu_path;
- device_t new;
- /* Build the cpu device path */
- cpu_path.type = DEVICE_PATH_APIC;
- cpu_path.u.apic.apic_id =
- (0x10 + i*0x10 + id.nodeid);
-
- new = alloc_dev(cpu->bus, &cpu_path);
- if (!new) {
- continue;
- }
-
- new->path.u.apic.node_id = cpu->path.u.apic.node_id;
- new->path.u.apic.core_id = i;
- /* Report what I have done */
- printk_debug("CPU: %s %s\n",
- dev_path(new), new->enabled?"enabled":"disabled");
- }
- }
-}
-
-struct node_core_id get_node_core_id(void)
-{
- struct node_core_id id;
- unsigned siblings;
- /* Get the apicid at reset */
- id.nodeid = (cpuid_ebx(1) >> 24) & 0xff;
- id.coreid = 0;
- /* Find out how many siblings we have */
- siblings = cpuid_ecx(0x80000008) & 0xff;
- if (siblings) {
- unsigned bits;
- msr_t msr;
- bits = 0;
- while ((1 << bits) <= siblings)
- bits++;
-
- msr = rdmsr(NB_CFG_MSR);
- if ((msr.hi >> (54-32)) & 1) {
- // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
- id.coreid = id.nodeid & ((1 << bits) - 1);
- id.nodeid >>= bits;
- } else {
- // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
- id.coreid = id.nodeid >> 3;
- id.nodeid &= 7;
- }
- } else {
- if (!is_cpu_pre_e0()) {
- id.nodeid >>= 1;
- }
- }
- return id;
-}
-
-unsigned int read_nb_cfg_54(void)
-{
- msr_t msr;
- msr = rdmsr(NB_CFG_MSR);
- return ( ( msr.hi >> (54-32)) & 1);
-}
+#include "dualcore_id.c"
static int get_max_siblings(int nodes)
{
@@ -161,14 +73,27 @@ unsigned get_apicid_base(unsigned ioapic_num)
siblings = get_max_siblings(nodes);
if(bsp_apic_id > 0) { // io apic could start from 0
- return 0;
+ return 0;
} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
- if(!disable_siblings) { return siblings + 1; }
- else { return 1; }
+ return 1;
}
nb_cfg_54 = read_nb_cfg_54();
+#if 0
+ //it is for all e0 single core and nc_cfg_54 low is set, but in the auto.c stage we do not set that bit for it.
+ if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
+ //we need to check if e0 single core is there
+ int i;
+ for(i=0; i<nodes; i++) {
+ if(is_e0_later_in_bsp(i)) {
+ siblings = 1;
+ break;
+ }
+ }
+ }
+#endif
+
//contruct apicid_base
if((!disable_siblings) && (siblings>0) ) {
@@ -193,4 +118,78 @@ unsigned get_apicid_base(unsigned ioapic_num)
return apicid_base;
}
+#if 0
+void amd_sibling_init(device_t cpu)
+{
+ unsigned i, siblings;
+ struct cpuid_result result;
+ unsigned nb_cfg_54;
+ struct node_core_id id;
+
+ /* On the bootstrap processor see if I want sibling cpus enabled */
+ if (first_time) {
+ first_time = 0;
+ get_option(&disable_siblings, "dual_core");
+ }
+ result = cpuid(0x80000008);
+ /* See how many sibling cpus we have */
+ /* Is dualcore supported */
+ siblings = (result.ecx & 0xff);
+ if ( siblings < 1) {
+ return;
+ }
+
+#if 1
+ printk_debug("CPU: %u %d siblings\n",
+ cpu->path.u.apic.apic_id,
+ siblings);
+#endif
+
+ nb_cfg_54 = read_nb_cfg_54();
+#if 1
+ id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
+
+ /* See if I am a sibling cpu */
+ //if ((cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) & siblings ) { // siblings = 1, 3, 7, 15,....
+ //if ( ( (cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) % (siblings+1) ) != 0 ) {
+ if(id.coreid != 0) {
+ if (disable_siblings) {
+ cpu->enabled = 0;
+ }
+ return;
+ }
+#endif
+
+ /* I am the primary cpu start up my siblings */
+
+ for(i = 1; i <= siblings; i++) {
+ struct device_path cpu_path;
+ device_t new;
+ /* Build the cpu device path */
+ cpu_path.type = DEVICE_PATH_APIC;
+ cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i * (nb_cfg_54?1:8);
+
+ /* See if I can find the cpu */
+ new = find_dev_path(cpu->bus, &cpu_path);
+ /* Allocate the new cpu device structure */
+ if(!new) {
+ new = alloc_dev(cpu->bus, &cpu_path);
+ new->enabled = 1;
+ new->initialized = 0;
+ }
+
+ new->path.u.apic.node_id = cpu->path.u.apic.node_id;
+ new->path.u.apic.core_id = i;
+
+#if 1
+ printk_debug("CPU: %u has sibling %u\n",
+ cpu->path.u.apic.apic_id,
+ new->path.u.apic.apic_id);
+#endif
+
+ if(new->enabled && !new->initialized)
+ start_cpu(new);
+ }
+}
+#endif
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c
index 89b81956eb..a1a898a4fa 100644
--- a/src/cpu/amd/dualcore/dualcore_id.c
+++ b/src/cpu/amd/dualcore/dualcore_id.c
@@ -1,7 +1,7 @@
/* 2004.12 yhlu add dual core support */
#include <arch/cpu.h>
-#include "cpu/amd/model_fxx/model_fxx_msr.h"
+#include <cpu/amd/model_fxx_msr.h>
static inline unsigned int read_nb_cfg_54(void)
{
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 71f64f4fe8..8d82b9aafa 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -5,30 +5,55 @@
* 2005.02 yhlu add e0 memory hole support
* Copyright 2005 AMD
- * 2005.08 yhlu add microcode support
-
+ * 2005.08 yhlu add microcode support
*/
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
-#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
+
#include "../../../northbridge/amd/amdk8/amdk8.h"
-#include "../../../northbridge/amd/amdk8/cpu_rev.c"
+
+#include <cpu/amd/model_fxx_rev.h>
#include <cpu/cpu.h>
-#include <cpu/amd/microcode.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/mem.h>
+
#include <cpu/amd/dualcore.h>
-#include "model_fxx_msr.h"
+#include <cpu/amd/model_fxx_msr.h>
+
+int is_e0_later_in_bsp(int nodeid)
+{
+ uint32_t val;
+ uint32_t val_old;
+ int e0_later;
+ if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
+ return !is_cpu_pre_e0();
+ }
+ // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
+ device_t dev;
+ dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
+ if(!dev) return 0;
+ val_old = pci_read_config32(dev, 0x80);
+ val = val_old;
+ val |= (1<<3);
+ pci_write_config32(dev, 0x80, val);
+ val = pci_read_config32(dev, 0x80);
+ e0_later = !!(val & (1<<3));
+ if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
+ pci_write_config32(dev, 0x80, val_old); // restore it
+ }
+
+ return e0_later;
+}
#define MCI_STATUS 0x401
@@ -53,7 +78,6 @@ static inline void wrmsr_amd(unsigned index, msr_t msr)
}
-
#define MTRR_COUNT 8
#define ZERO_CHUNK_KB 0x800UL /* 2M */
#define TOLM_KB 0x400000UL
@@ -151,9 +175,11 @@ static void set_init_ecc_mtrrs(void)
enable_cache();
}
+
static void init_ecc_memory(unsigned node_id)
{
unsigned long startk, begink, endk;
+ unsigned long hole_startk = 0;
unsigned long basek;
struct mtrr_state mtrr_state;
device_t f1_dev, f2_dev, f3_dev;
@@ -198,6 +224,18 @@ static void init_ecc_memory(unsigned node_id)
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
+#if K8_HW_MEM_HOLE_SIZEK != 0
+ if (!is_cpu_pre_e0())
+ {
+
+ uint32_t val;
+ val = pci_read_config32(f1_dev, 0xf0);
+ if(val & 1) {
+ hole_startk = ((val & (0xff<<24)) >> 10);
+ }
+ }
+#endif
+
/* Don't start too early */
begink = startk;
@@ -221,8 +259,15 @@ static void init_ecc_memory(unsigned node_id)
unsigned long size;
void *addr;
+#if K8_HW_MEM_HOLE_SIZEK != 0
+ if ( hole_startk != 0 ) {
+ if ((basek >= hole_startk) && (basek < 4*1024*1024)) continue;
+ }
+#endif
+
/* Report every 64M */
if ((basek % (64*1024)) == 0) {
+
/* Restore the normal state */
map_2M_page(0);
restore_mtrr_state(&mtrr_state);
@@ -234,6 +279,7 @@ static void init_ecc_memory(unsigned node_id)
/* Return to the initialization state */
set_init_ecc_mtrrs();
disable_lapic();
+
}
limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
@@ -304,7 +350,7 @@ static inline void k8_errata(void)
* FIXME this is only needed if ECC is enabled.
*/
msr.hi |= 1 << (36 - 32);
- }
+ }
wrmsr(NB_CFG_MSR, msr);
}
@@ -324,7 +370,6 @@ static inline void k8_errata(void)
/* Erratum 91 prefetch miss is handled in the kernel */
-
/* Erratum 106 ... */
msr = rdmsr_amd(LS_CFG_MSR);
msr.lo |= 1 << 25;
@@ -335,49 +380,39 @@ static inline void k8_errata(void)
msr.hi |= 1 << (43 - 32);
wrmsr_amd(BU_CFG_MSR, msr);
- if (is_cpu_pre_e0() && !is_cpu_pre_d0()) {
+ if(is_cpu_d0()) {
/* Erratum 110 ...*/
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
msr.hi |=1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
}
- if (!is_cpu_pre_e0()) {
+ if (!is_cpu_pre_e0())
+ {
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |=1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
-
- /* Erratum 113 ... */
- msr = rdmsr_amd(BU_CFG_MSR);
- msr.hi |= (1 << 16);
- wrmsr_amd(BU_CFG_MSR, msr);
}
/* Erratum 122 */
- if (!is_cpu_pre_c0()) {
- msr = rdmsr(HWCR_MSR);
- msr.lo |= 1 << 6;
- wrmsr(HWCR_MSR, msr);
- }
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= 1 << 6;
+ wrmsr(HWCR_MSR, msr);
- /* Erratum 123? dual core deadlock? */
-
- /* Erratum 131 */
- msr = rdmsr(NB_CFG_MSR);
- msr.lo |= 1 << 20;
- wrmsr(NB_CFG_MSR, msr);
-
}
+
extern void model_fxx_update_microcode(unsigned cpu_deviceid);
-void model_fxx_init(device_t cpu)
+void model_fxx_init(device_t dev)
{
unsigned long i;
msr_t msr;
struct node_core_id id;
- unsigned equivalent_processor_rev_id;
+#if CONFIG_LOGICAL_CPUS == 1
+ unsigned siblings;
+#endif
/* Turn on caching if we haven't already */
x86_enable_cache();
@@ -385,8 +420,8 @@ void model_fxx_init(device_t cpu)
x86_mtrr_check();
/* Update the microcode */
- model_fxx_update_microcode(cpu->device);
-
+ model_fxx_update_microcode(dev->device);
+
disable_cache();
/* zero the machine check error status registers */
@@ -403,18 +438,37 @@ void model_fxx_init(device_t cpu)
/* Enable the local cpu apics */
setup_lapic();
- /* Find our node and core */
- id = get_node_core_id();
+#if CONFIG_LOGICAL_CPUS == 1
+ siblings = cpuid_ecx(0x80000008) & 0xff;
- /* Is this a bad location? In particular can another node prefetch
+ if(siblings>0) {
+ msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+ msr.lo |= 1 << 28;
+ wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+ msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
+ msr.lo = (siblings+1)<<16;
+ wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
+
+ msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+ msr.hi |= 1<<(33-32);
+ wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+ }
+
+#endif
+
+ id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
+
+ /* Is this a bad location? In particular can another node prefecth
* data from this node before we have initialized it?
*/
- if (id.coreid == 0) {
- init_ecc_memory(id.nodeid); // only do it for core 0
- }
+ if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
+
+#if CONFIG_LOGICAL_CPUS==1
+ /* Start up my cpu siblings */
+// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
+#endif
- /* Deal with sibling cpus */
- amd_sibling_init(cpu, id);
}
static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/amd/model_fxx/model_fxx_msr.h b/src/cpu/amd/model_fxx/model_fxx_msr.h
index b4795cbbb2..e69de29bb2 100644
--- a/src/cpu/amd/model_fxx/model_fxx_msr.h
+++ b/src/cpu/amd/model_fxx/model_fxx_msr.h
@@ -1,21 +0,0 @@
-#ifndef CPU_AMD_MODEL_FXX_MSR_H
-#define CPU_AMD_MODEL_FXX_MSR_H
-
-#define HWCR_MSR 0xC0010015
-#define NB_CFG_MSR 0xC001001f
-#define LS_CFG_MSR 0xC0011020
-#define IC_CFG_MSR 0xC0011021
-#define DC_CFG_MSR 0xC0011022
-#define BU_CFG_MSR 0xC0011023
-
-
-#define CPU_ID_FEATURES_MSR 0xc0011004
-
-/* D0 only */
-#define CPU_ID_HYPER_EXT_FEATURES 0xc001100d
-/* E0 only */
-#define LOGICAL_CPUS_NUM_MSR 0xc001100d
-
-#define CPU_ID_EXT_FEATURES_MSR 0xc0011005
-
-#endif /* CPU_AMD_MODEL_FXX_MSR_H */