summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorTristan Corrick <tristan@corrick.kiwi>2018-10-31 02:27:12 +1300
committerNico Huber <nico.h@gmx.de>2018-11-01 22:23:21 +0000
commitfdf907e4405e5df84e9d5a29735e0506782d9c6d (patch)
tree76da8301ef861c1827d5280a67e75160019dda0f /src/cpu
parentba8ead817dad9be5e3afa0a702d888d4a48a640d (diff)
downloadcoreboot-fdf907e4405e5df84e9d5a29735e0506782d9c6d.tar.xz
cpu/intel/haswell: Only change the slow ramp rate for ULT CPUs
On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow ramp rate during `initialize_vr_config()` results in the following exception, causing the system to hang. CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000 edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90 So, only change this setting for Haswell ULT CPUs, as suggested by the BIOS Writer's guide. Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29384 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/haswell/haswell_init.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index c67ef1438d..2340dd0b03 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -333,9 +333,11 @@ static void initialize_vr_config(void)
msr.hi &= ~(1 << (51 - 32));
/* Enable decay mode on C-state entry. */
msr.hi |= (1 << (52 - 32));
- /* Set the slow ramp rate to be fast ramp rate / 4 */
- msr.hi &= ~(0x3 << (53 - 32));
- msr.hi |= (0x01 << (53 - 32));
+ if (haswell_is_ult()) {
+ /* Set the slow ramp rate to be fast ramp rate / 4 */
+ msr.hi &= ~(0x3 << (53 - 32));
+ msr.hi |= (0x01 << (53 - 32));
+ }
/* Set MIN_VID (31:24) to allow CPU to have full control. */
msr.lo &= ~0xff000000;
wrmsr(MSR_VR_MISC_CONFIG, msr);