summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2011-02-10 07:51:51 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2011-02-10 07:51:51 +0000
commit1df854248b60b93aef9e4c37bd6da95371a6d867 (patch)
tree97ed6fe5731682f6691c183414ac3c4e0cd6bbf3 /src/cpu
parent31e0deac0e8771a0c98d9463fd7caa101ffb3be1 (diff)
downloadcoreboot-1df854248b60b93aef9e4c37bd6da95371a6d867.tar.xz
Implemented workaround for erratum 169, obsoleting erratum 131.
Workaround for 131 removed. Changed workaround for erratum 110 to only include pre-revision-F processors. For details, check AMD publications: #25759 (Errata for Fam F pre-revision F processors) #33610 (Errata for Fam F revision F and later processor) Based on work and previous patches by: Rudolf Marek <r.marek@assembler.cz> Josef Kellermann <seppk@arcor.de> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_init.c36
1 files changed, 22 insertions, 14 deletions
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index ea00f47837..a5112b3823 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -411,33 +411,35 @@ static inline void k8_errata(void)
msr.hi |= 1 << (43 - 32);
wrmsr_amd(BU_CFG_MSR, msr);
+ /* Erratum 110 */
+ /* This erratum applies to D0 thru E6 revisions
+ * Revision F and later are unaffected. There are two fixes
+ * depending on processor revision.
+ */
if (is_cpu_d0()) {
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
msr.hi |= 1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
}
-#endif
-#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
-#endif
{
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
-
+#endif
+
+
#if CONFIG_K8_REV_F_SUPPORT == 0
- /* I can't touch this msr on early buggy cpus */
+ /* I can't touch this msr on early buggy cpus */
if (!is_cpu_pre_b3())
#endif
{
-
- /* Erratum 89 ... */
msr = rdmsr(NB_CFG_MSR);
- msr.lo |= 1 << 3;
+
#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
/* D0 later don't need it */
@@ -448,6 +450,18 @@ static inline void k8_errata(void)
msr.hi |= 1 << (36 - 32);
}
#endif
+ /* Erratum 89 ... */
+ /* Erratum 89 is mistakenly labeled as 88 in AMD pub #25759
+ * It is correctly labeled as 89 on page 49 of the document
+ * and in AMD pub#33610
+ */
+ msr.lo |= 1 << 3;
+ /* Erratum 169 */
+ /* This supersedes erratum 131; 131 should not be applied with 169
+ * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
+ */
+ msr.hi |= 1;
+
wrmsr(NB_CFG_MSR, msr);
}
/* Erratum 122 */
@@ -455,12 +469,6 @@ static inline void k8_errata(void)
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
-#if CONFIG_K8_REV_F_SUPPORT == 1
- /* Erratum 131... */
- msr = rdmsr(NB_CFG_MSR);
- msr.lo |= 1 << 20;
- wrmsr(NB_CFG_MSR, msr);
-#endif
}