- Fix UDELAY options and HAVE_INIT_TIMER [kconfig]

  (defaults to UDELAY_IO again, like newconfig)
- Use UDELAY_TSC on Via C7 [kconfig]
- Support Tinybootblock on Intel CPUs
- set XIP location correctly for Tinybootblock on Intel
- provide correct XIP location in Tinybootblock configuration
- Make kontron/986lcd-m use Tinybootblock
- Some kconfig fixes to kontron/986lcd-m [kconfig]

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 29 insertions, 3 deletions

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index a216aa3295..dec09fee65 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -114,7 +114,13 @@ clear_mtrrs:
 	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
index 7808d56f31..d52bf0b178 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
@@ -25,6 +25,7 @@ void stage1_main(unsigned long bist)
 {
 	unsigned int cpu_reset = 0;
 
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -46,6 +47,7 @@ void stage1_main(unsigned long bist)
                 );
  fallback_image:
 #endif
+#endif
 
 	real_main(bist);
 
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 9623dc4086..28d510066d 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -104,7 +104,13 @@ clear_mtrrs:
 	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
index a22978e051..fcdd3f2e19 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
@@ -27,6 +27,7 @@ void stage1_main(unsigned long bist)
 {
 	unsigned int cpu_reset = 0;
 
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@ void stage1_main(unsigned long bist)
                 );
  fallback_image:
 #endif
+#endif
 
 	real_main(bist);
 
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 5082a2e4db..a664da2f87 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -111,7 +111,13 @@ clear_mtrrs:
 	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c
index a22978e051..fcdd3f2e19 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6fx/cache_as_ram_disable.c
@@ -27,6 +27,7 @@ void stage1_main(unsigned long bist)
 {
 	unsigned int cpu_reset = 0;
 
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@ void stage1_main(unsigned long bist)
                 );
  fallback_image:
 #endif
+#endif
 
 	real_main(bist);
 
diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig
index 22daaf434f..8a2fe88a44 100644
--- a/src/cpu/via/model_c7/Kconfig
+++ b/src/cpu/via/model_c7/Kconfig
@@ -1,2 +1,3 @@
 config CPU_VIA_C7
 	bool
+	select UDELAY_TSC
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index a3b9330e64..59f27de794 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -8,6 +8,7 @@ config WAIT_BEFORE_CPUS_INIT
 
 config UDELAY_IO
 	bool
+	default y if !UDELAY_LAPIC && !UDELAY_TSC
 	default n
 
 config UDELAY_LAPIC