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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-27 23:53:11 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-27 23:53:11 +0000
commit40f9b4b07e98f35336458cdc7a9a6257fb842470 (patch)
tree0d1a7e56dd56b63e17f07e9fbce37870d44ebbf0 /src/cpu
parent1d80e5101772220213f64a8845b21fa063710995 (diff)
downloadcoreboot-40f9b4b07e98f35336458cdc7a9a6257fb842470.tar.xz
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3x[84:80], ACPI Power State Control Registers, to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/model_10xxx/fidvid.c16
1 files changed, 9 insertions, 7 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 8f102c5831..7ce2aea193 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -257,7 +257,6 @@ static void config_power_ctrl_misc_reg(device_t dev) {
pci_write_config32(dev, 0xD8, dword);
}
}
-
static void config_nb_syn_ptr_adj(device_t dev) {
/* Note the following settings are additional from the ported
@@ -269,6 +268,14 @@ static void config_nb_syn_ptr_adj(device_t dev) {
}
+static void config_acpi_pwr_state_ctrl_regs(device_t dev) {
+ /* Rev B settings - FIXME: support other revs. */
+ u32 dword = 0xA0E641E6;
+ pci_write_config32(dev, 0x84, dword);
+ dword = 0xE600A681;
+ pci_write_config32(dev, 0x80, dword);
+}
+
static void prep_fid_change(void)
{
u32 dword;
@@ -295,12 +302,7 @@ static void prep_fid_change(void)
config_nb_syn_ptr_adj(dev);
- /* Rev B settings - FIXME: support other revs. */
- dword = 0xA0E641E6;
- pci_write_config32(dev, 0x84, dword);
-
- dword = 0xE600A681;
- pci_write_config32(dev, 0x80, dword);
+ config_acpi_pwr_state_ctrl_regs(dev);
dword = pci_read_config32(dev, 0x80);
printk(BIOS_DEBUG, " F3x80: %08x \n", dword);