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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-05-25 08:52:07 +0300
committerNico Huber <nico.h@gmx.de>2020-06-15 18:34:45 +0000
commit49c44cdccb936bf1179402b5927a1f477ad4e752 (patch)
treec0bf42d989c20188fc9bac8b6bfd3c5ab99cf00b /src/cpu
parentc36469e0b12f41b624eea072014b715b3c564513 (diff)
downloadcoreboot-49c44cdccb936bf1179402b5927a1f477ad4e752.tar.xz
arch/x86: Remove XIP_ROM_SIZE
When adding XIP stages on x86, the -P parameter was used to pass a page size that covers the entire file to add. The same can now be achieved with --pow2page and we no longer need to define a static Konfig for the purpose. TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and inspect the generated make.log files. The effective pagesize is reduced from 64kB to 16kB for asus/p2b giving more freedom for the stage placement inside CBFS. Pagesize remained at 64kB for lenovo/x60. Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/Kconfig5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 4260278e02..07dfe45e64 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -70,11 +70,6 @@ config NO_FIXED_XIP_ROM_SIZE
to unnecessary alignment constraints in cbfs for romstage.
Therefore, allow those chipsets a path to not be burdened.
-config XIP_ROM_SIZE
- hex
- depends on !NO_FIXED_XIP_ROM_SIZE
- default 0x10000
-
config SETUP_XIP_CACHE
bool
depends on !NO_XIP_EARLY_STAGES