Remove:

- CONFIG_CBFS
- anything that's conditional on CONFIG_CBFS == 0
- files that were only included for CONFIG_CBFS == 0
In particular:
- elfboot
- stream boot code
- mini-filo and filesystems (depends on stream boot code)

After this commit, there is no way to build an image that is not using
CBFS anymore.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 8 insertions, 81 deletions

diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c
index 79cae6bc83..a391ec59b4 100644
--- a/src/cpu/amd/car/copy_and_run.c
+++ b/src/cpu/amd/car/copy_and_run.c
@@ -3,16 +3,15 @@
    2006/05/02 - stepan: move nrv2b to an extra file.
 */
 
-#if CONFIG_CBFS == 1
 void cbfs_and_run_core(const char*, unsigned ebp);
 
 static void copy_and_run(void)
 {
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_and_run_core("fallback/coreboot_ram", 0);
-# else
+#else
       	cbfs_and_run_core("normal/coreboot_ram", 0);
-# endif
+#endif
 }
 
 #if CONFIG_AP_CODE_IN_CAR == 1
@@ -26,38 +25,3 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr)
 # endif
 }
 #endif
-
-#else
-void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
-
-extern u8 _liseg, _iseg, _eiseg;
-
-static void copy_and_run(void)
-{
-	uint8_t *src, *dst; 
-        unsigned long ilen;
-
-	src = &_liseg;
-	dst = &_iseg;
-	ilen = &_eiseg - dst;
-
-	copy_and_run_core(src, dst, ilen, 0);
-}
-
-#if CONFIG_AP_CODE_IN_CAR == 1
-
-extern u8 _liseg_apc, _iseg_apc, _eiseg_apc;
-
-static void copy_and_run_ap_code_in_car(unsigned ret_addr)
-{
-        uint8_t *src, *dst;
-        unsigned long ilen;
-
-	src = &_liseg_apc;
-	dst = &_iseg_apc;
-	ilen = &_eiseg_apc - dst;
-
-	copy_and_run_core(src, dst, ilen, ret_addr);
-}
-#endif
-#endif
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
index fcd7bdc04c..ee4902a269 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -222,19 +222,8 @@ __main:
 	movl	$0x4000000, %esp
 	movl	%esp, %ebp
 	pushl	%esi
-#if CONFIG_CBFS == 1
 	pushl $str_coreboot_ram_name
 	call cbfs_and_run_core
-#else
-	movl	$_liseg, %esi
-	movl	$_iseg,  %edi
-	movl	$_eiseg, %ecx
-	subl	%edi, %ecx
-	pushl	%ecx
-	pushl	%edi
-	pushl	%esi
-	call copy_and_run_core
-#endif
 
 .Lhlt:
 	intel_chip_post_macro(0xee)	/* post fail ee */
@@ -295,10 +284,8 @@ str_pre_main:        .string "Jumping to coreboot.\r\n"
 .previous
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
-#if CONFIG_CBFS == 1
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 str_coreboot_ram_name:	.string "fallback/coreboot_ram"
-# else
+#else
 str_coreboot_ram_name:	.string "normal/coreboot_ram"
-# endif
 #endif
diff --git a/src/cpu/x86/car/copy_and_run.c b/src/cpu/x86/car/copy_and_run.c
index 7ff63c5e0c..7257c4f6bc 100644
--- a/src/cpu/x86/car/copy_and_run.c
+++ b/src/cpu/x86/car/copy_and_run.c
@@ -2,7 +2,6 @@
    (Written by Patrick Georgi <patrick.georgi@coresystems.de> for coresystems GmbH
 */
 
-#if CONFIG_CBFS == 1
 void cbfs_and_run_core(char*, unsigned ebp);
 
 static void copy_and_run(unsigned cpu_reset)
@@ -10,32 +9,9 @@ static void copy_and_run(unsigned cpu_reset)
 	if (cpu_reset == 1) cpu_reset = -1;
 	else cpu_reset = 0;
 
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_and_run_core("fallback/coreboot_ram", cpu_reset);
-# else
-	cbfs_and_run_core("normal/coreboot_ram", cpu_reset);
-# endif
-}
-
 #else
-void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
-
-extern u8 _liseg, _iseg, _eiseg;
-
-static void copy_and_run(unsigned cpu_reset)
-{
-	uint8_t *src, *dst; 
-        unsigned long ilen;
-
-
-	src = &_liseg;
-	dst = &_iseg;
-	ilen = &_eiseg - dst;
-
-	if (cpu_reset == 1) cpu_reset = -1;
-	else cpu_reset = 0;
-
-	copy_and_run_core(src, dst, ilen, cpu_reset);
-}
+	cbfs_and_run_core("normal/coreboot_ram", cpu_reset);
 #endif
-
+}