diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-27 20:05:22 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-04-10 16:04:59 +0000 |
| commit | 7811a45553cf750a19040ff9e2532f7f5ba5ed78 (patch) | |
| tree | ea803187ebd3cb8601a8d19d0b224d98d2e3e623 /src/cpu | |
| parent | 528b471f94f5c4957e941b7547f583e6ce4db765 (diff) | |
| download | coreboot-7811a45553cf750a19040ff9e2532f7f5ba5ed78.tar.xz | |
cpu/intel/haswell: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I5fb31f88bbf7c2f1e44924ca2d3169257a9598dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index f4b38e5a81..8ba1c937f0 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -88,7 +88,7 @@ static int pcode_ready(void) wait_count = 0; do { - if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) + if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) return 0; wait_count += delay_step; udelay(delay_step); @@ -107,23 +107,23 @@ static void calibrate_24mhz_bclk(void) } /* A non-zero value initiates the PCODE calibration. */ - MCHBAR32(BIOS_MAILBOX_DATA) = ~0; - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; + mchbar_write32(BIOS_MAILBOX_DATA, ~0); + mchbar_write32(BIOS_MAILBOX_INTERFACE, + MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL); if (pcode_ready() < 0) { printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); return; } - err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; + err_code = mchbar_read32(BIOS_MAILBOX_INTERFACE) & 0xff; printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code); /* Read the calibrated value. */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; + mchbar_write32(BIOS_MAILBOX_INTERFACE, + MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION); if (pcode_ready() < 0) { printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); @@ -131,7 +131,7 @@ static void calibrate_24mhz_bclk(void) } printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); + mchbar_read32(BIOS_MAILBOX_DATA)); } static u32 pcode_mailbox_read(u32 command) @@ -142,7 +142,7 @@ static u32 pcode_mailbox_read(u32 command) } /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY); if (pcode_ready() < 0) { printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); @@ -150,7 +150,7 @@ static u32 pcode_mailbox_read(u32 command) } /* Read mailbox */ - return MCHBAR32(BIOS_MAILBOX_DATA); + return mchbar_read32(BIOS_MAILBOX_DATA); } static int pcode_mailbox_write(u32 command, u32 data) @@ -160,10 +160,10 @@ static int pcode_mailbox_write(u32 command, u32 data) return -1; } - MCHBAR32(BIOS_MAILBOX_DATA) = data; + mchbar_write32(BIOS_MAILBOX_DATA, data); /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY); if (pcode_ready() < 0) { printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); @@ -365,12 +365,12 @@ void set_power_limits(u8 power_limit_1_time) wrmsr(MSR_PKG_POWER_LIMIT, limit); /* Set power limit values in MCHBAR as well */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; + mchbar_write32(MCH_PKG_POWER_LIMIT_LO, limit.lo); + mchbar_write32(MCH_PKG_POWER_LIMIT_HI, limit.hi); /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); + msr.lo = mchbar_read32(MCH_DDR_POWER_LIMIT_LO); + msr.hi = mchbar_read32(MCH_DDR_POWER_LIMIT_HI); wrmsr(MSR_DDR_RAPL_LIMIT, msr); /* Use nominal TDP values for CPUs with configurable TDP */ |