diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-15 06:08:15 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 00:19:08 +0200 |
| commit | a969ed34dbaebc595e298f60810669f0e8a3bcd2 (patch) | |
| tree | f55750965fb4f87db09d73e4571f28eb20a59964 /src/cpu | |
| parent | 465eff61f4f0f730476aa7afe8819f1e6b118068 (diff) | |
| download | coreboot-a969ed34dbaebc595e298f60810669f0e8a3bcd2.tar.xz | |
Move definitions of HIGH_MEMORY_SAVE
This is more of ACPI S3 resume and x86 definition than CBMEM.
Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15190
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 492728dcf9..5f486f2fea 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9c08aa16ba..b8ce5d6d43 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -24,6 +24,7 @@ #include <halt.h> #include <lib.h> #include <timestamp.h> +#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pci_def.h> diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index eef12b7e8d..358ba75e04 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -18,6 +18,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #include <cbmem.h> +#include <arch/acpi.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |