This patch adds support for the AMD Geode LX CPU. (rediffed)

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 627 insertions, 530 deletions

diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
new file mode 100644
index 0000000000..fa90c5bf7f
--- /dev/null
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -0,0 +1,370 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/
+
+
+#define	LX_STACK_BASE		DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
+#define	LX_STACK_END		LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
+
+#define	LX_NUM_CACHELINES	0x080	/* there are 128lines per way */
+#define	LX_CACHELINE_SIZE	0x020	/* there are 32bytes per line */
+#define	LX_CACHEWAY_SIZE	(LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
+#define	CR0_CD				0x40000000	/* bit 30 = Cache Disable */
+#define	CR0_NW				0x20000000	/* bit 29 = Not Write Through */
+#include <cpu/amd/lxdef.h>
+/***************************************************************************
+/**
+/**	DCacheSetup
+/**
+/**	Setup data cache for  use as RAM for a stack.
+/**
+/***************************************************************************/
+DCacheSetup:
+
+	invd
+	/* set cache properties */
+	movl	$CPU_RCONF_DEFAULT, %ecx
+	rdmsr
+	movl	$0x010010000, %eax		/*1MB system memory in write back 1|00100|00 */
+	wrmsr
+
+	/* in LX DCDIS is set after POR which disables the cache..., clear this bit */
+	movl	CPU_DM_CONFIG0,%ecx
+	rdmsr
+	andl	$(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax	/* TODO: make consistent with i$ init,	either whole reg = 0,  or just this bit... */
+	wrmsr
+
+	/* get cache timing params from BIOS config data locations and apply */
+	/* fix delay controls for DM and IM arrays */
+	/* fix delay controls for DM and IM arrays */
+	movl	$CPU_BC_MSS_ARRAY_CTL0, %ecx
+	xorl	%edx, %edx
+	movl	$0x2814D352, %eax
+	wrmsr
+
+	movl	$CPU_BC_MSS_ARRAY_CTL1, %ecx
+	xorl	%edx, %edx
+	movl	$0x1068334D, %eax
+	wrmsr
+
+	movl	$CPU_BC_MSS_ARRAY_CTL2, %ecx
+	movl	$0x00000106, %edx
+	movl	$0x83104104, %eax
+	wrmsr
+
+	movl	$GLCP_FIFOCTL, %ecx
+	rdmsr
+	movl	$0x00000005, %edx
+	wrmsr
+
+	/* Enable setting */
+	movl	$CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
+	xorl	%edx, %edx
+	movl	$0x01, %eax
+	wrmsr
+
+	/* Get cleaned up. */
+	xorl	%edi, %edi
+	xorl	%esi, %esi
+	xorl	%ebp, %ebp
+
+	/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */
+	/* remember,  there is NO stack yet... */
+
+	/* Tell cache we want to fill WAY 0 starting at the top */
+	xorl	%edx, %edx
+	xorl	%eax, %eax
+	movl	$CPU_DC_INDEX, %ecx
+	wrmsr
+
+	/* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
+	movl	$LX_STACK_BASE, %ebp	/* init to start address */
+	orl		$1, %ebp				/* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
+
+	/* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
+	movl	$LX_NUM_CACHELINES, %edi
+DCacheSetupFillWay:
+
+	/* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
+	/* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
+	movw	$0x04, %si
+	xorl	%edx, %edx
+	xorl	%eax, %eax
+	movl	$CPU_DC_DATA, %ecx
+DCacheSetup_quadWordLoop:
+	wrmsr
+	decw	%si
+	jnz	DCacheSetup_quadWordLoop
+
+	/* Set the tag for this line,  need to do this for every new cache line to validate it! */
+	/* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
+	xorl	%edx, %edx
+	movl	%ebp, %eax
+	movl	$CPU_DC_TAG, %ecx
+	wrmsr
+
+	/* switch to next line */
+	/* lines are in Bits10:4 */
+	/* when index is crossing 0x7F -> 0x80	writing a RSVD bit as 0x80 is not a valid CL anymore! */
+	movl	$CPU_DC_INDEX, %ecx
+	rdmsr
+	addl	$0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */
+	wrmsr
+
+	decl	%edi
+	jnz	DCacheSetupFillWay
+
+	/* 1 Way has been filled,  forward start address for next Way,	terminate if we have reached end of desired address range */
+	addl	$LX_CACHEWAY_SIZE, %ebp
+	cmpl	$LX_STACK_END, %ebp
+	jge	leave_DCacheSetup
+	movl	$LX_NUM_CACHELINES, %edi
+
+	/* switch to next way */
+	movl	$CPU_DC_INDEX, %ecx
+	rdmsr
+	addl	$0x01, %eax
+	andl	$0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */
+	wrmsr
+
+	jmp	DCacheSetupFillWay
+
+leave_DCacheSetup:
+	xorl	%edi, %edi
+	xorl	%esi, %esi
+	xorl	%ebp, %ebp
+
+	/* Disable the cache,  but ... DO NOT INVALIDATE the tags. */
+	/* Memory reads and writes will all hit in the cache. */
+	/* Cache updates and memory write-backs will not occur ! */
+	movl	%cr0, %eax
+	orl		$(CR0_CD + CR0_NW), %eax	/* set the CD and NW bits */
+	movl	%eax, %cr0
+
+	/* Now point sp to the cached stack. */
+	/* The stack will be fully functional at this location. No system memory is required at all ! */
+	/* set up the stack pointer */
+	movl	$LX_STACK_END, %eax
+	movl	%eax, %esp
+
+	/* test the stack*/
+	movl	$0x0F0F05A5A, %edx
+	pushl	%edx
+	popl	%ecx
+	cmpl	%ecx, %edx
+	je	DCacheSetupGood
+	movb	$0xC5, %al
+	outb	%al, $0x80
+DCacheSetupBad:
+	hlt		/* issues */
+	jmp DCacheSetupBad
+DCacheSetupGood:
+
+	/* Go do early init and memory setup */
+	call	cache_as_ram_main
+
+	/* If you wanted to maintain the stack in memory you would need to set the tags as dirty
+	  so the wbinvd would push out the old stack contents to memory */
+	/* Clear the cache, the following code from crt0.S.lb will setup a new stack*/
+	wbinvd
+
+/* the following code is from crt0.S.lb */
+/* This takes the place of the post-CAR funtions that the K8 uses to setup the stack and copy LB low.*/
+
+#ifndef CONSOLE_DEBUG_TX_STRING
+	/* uses:	 esp, ebx, ax, dx */
+# define __CRT_CONSOLE_TX_STRING(string) \
+	mov	string, %ebx	; \
+	CALLSP(crt_console_tx_string)
+
+# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+#  define CONSOLE_DEBUG_TX_STRING(string)        __CRT_CONSOLE_TX_STRING(string)
+# else
+#  define CONSOLE_DEBUG_TX_STRING(string)
+# endif
+#endif
+
+	/* clear boot_complete flag */
+	xorl	%ebp, %ebp
+__main:
+	CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
+
+	/*
+	 *	Copy data into RAM and clear the BSS. Since these segments
+	 *	isn\'t really that big we just copy/clear using bytes, not
+	 *	double words.
+	 */
+	intel_chip_post_macro(0x11)		/* post 11 */
+
+	cld				/* clear direction flag */
+
+	/* copy linuxBIOS from it's initial load location to
+	 * the location it is compiled to run at.
+	 * Normally this is copying from FLASH ROM to RAM.
+	 */
+#if !CONFIG_COMPRESS
+	movl	$_liseg, %esi
+	movl	$_iseg,  %edi
+	movl	$_eiseg, %ecx
+	subl	%edi, %ecx
+	rep	movsb
+#else
+	leal	4+_liseg, %esi
+	leal	_iseg, %edi
+	movl	%ebp, %esp	/* preserve %ebp */
+	movl	$-1, %ebp	/* last_m_off = -1 */
+	jmp	dcl1_n2b
+
+/* ------------- DECOMPRESSION -------------
+
+ Input:
+   %esi - source
+   %edi - dest
+   %ebp - -1
+   cld
+
+ Output:
+   %eax - 0
+   %ecx - 0
+*/
+
+.macro getbit bits
+.if	\bits == 1
+	addl	%ebx, %ebx
+	jnz	1f
+.endif
+	movl	(%esi), %ebx
+	subl	$-4, %esi	/* sets carry flag */
+	adcl	%ebx, %ebx
+1:
+.endm
+
+decompr_literals_n2b:
+	movsb
+
+decompr_loop_n2b:
+	addl	%ebx, %ebx
+	jnz	dcl2_n2b
+dcl1_n2b:
+	getbit	32
+dcl2_n2b:
+	jc	decompr_literals_n2b
+	xorl	%eax, %eax
+	incl	%eax		/* m_off = 1 */
+loop1_n2b:
+	getbit	1
+	adcl	%eax, %eax	/* m_off = m_off*2 + getbit() */
+	getbit	1
+	jnc	loop1_n2b	/* while(!getbit()) */
+	xorl	%ecx, %ecx
+	subl	$3, %eax
+	jb	decompr_ebpeax_n2b	/* if (m_off == 2) goto decompr_ebpeax_n2b ? */
+	shll	$8, %eax
+	movb	(%esi), %al	/* m_off = (m_off - 3)*256 + src[ilen++] */
+	incl	%esi
+	xorl	$-1, %eax
+	jz	decompr_end_n2b	/* if (m_off == 0xffffffff) goto decomp_end_n2b */
+	movl	%eax, %ebp	/* last_m_off = m_off ?*/
+decompr_ebpeax_n2b:
+	getbit	1
+	adcl	%ecx, %ecx	/* m_len = getbit() */
+	getbit	1
+	adcl	%ecx, %ecx	/* m_len = m_len*2 + getbit()) */
+	jnz	decompr_got_mlen_n2b	/* if (m_len == 0) goto decompr_got_mlen_n2b */
+	incl	%ecx		/* m_len++ */
+loop2_n2b:
+	getbit	1
+	adcl	%ecx, %ecx	/* m_len = m_len*2 + getbit() */
+	getbit	1
+	jnc	loop2_n2b	/* while(!getbit()) */
+	incl	%ecx
+	incl	%ecx		/* m_len += 2 */
+decompr_got_mlen_n2b:
+	cmpl	$-0xd00, %ebp
+	adcl	$1, %ecx	/* m_len = m_len + 1 + (last_m_off > 0xd00) */
+	movl	%esi, %edx
+	leal	(%edi,%ebp), %esi	/* m_pos = dst + olen + -m_off  */
+	rep
+	movsb			/* dst[olen++] = *m_pos++ while(m_len > 0) */
+	movl	%edx, %esi
+	jmp	decompr_loop_n2b
+decompr_end_n2b:
+	intel_chip_post_macro(0x12)		/* post 12 */
+
+	movl	%esp, %ebp
+#endif
+
+	CONSOLE_DEBUG_TX_STRING($str_pre_main)
+	leal	_iseg, %edi
+	jmp	*%edi
+
+.Lhlt:
+	intel_chip_post_macro(0xee)	/* post fail ee */
+	hlt
+	jmp	.Lhlt
+
+#ifdef __CRT_CONSOLE_TX_STRING
+	/* Uses esp, ebx, ax, dx  */
+crt_console_tx_string:
+	mov	(%ebx), %al
+	inc	%ebx
+	cmp	$0, %al
+	jne	9f
+	RETSP
+9:
+/* Base Address */
+#ifndef TTYS0_BASE
+#define TTYS0_BASE	0x3f8
+#endif
+/* Data */
+#define TTYS0_RBR (TTYS0_BASE+0x00)
+
+/* Control */
+#define TTYS0_TBR TTYS0_RBR
+#define TTYS0_IER (TTYS0_BASE+0x01)
+#define TTYS0_IIR (TTYS0_BASE+0x02)
+#define TTYS0_FCR TTYS0_IIR
+#define TTYS0_LCR (TTYS0_BASE+0x03)
+#define TTYS0_MCR (TTYS0_BASE+0x04)
+#define TTYS0_DLL TTYS0_RBR
+#define TTYS0_DLM TTYS0_IER
+
+/* Status */
+#define TTYS0_LSR (TTYS0_BASE+0x05)
+#define TTYS0_MSR (TTYS0_BASE+0x06)
+#define TTYS0_SCR (TTYS0_BASE+0x07)
+
+	mov	%al, %ah
+10:	mov	$TTYS0_LSR, %dx
+	inb	%dx, %al
+	test	$0x20, %al
+	je	10b
+	mov	$TTYS0_TBR, %dx
+	mov	%ah, %al
+	outb	%al, %dx
+
+	jmp crt_console_tx_string
+#endif /* __CRT_CONSOLE_TX_STRING */
+
+#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+.section ".rom.data"
+str_copying_to_ram:  .string "Copying LinuxBIOS to ram.\r\n"
+str_pre_main:        .string "Jumping to LinuxBIOS.\r\n"
+.previous
+
+#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c
index af5a3f03bc..ce81929b18 100644
--- a/src/cpu/amd/model_lx/cpubug.c
+++ b/src/cpu/amd/model_lx/cpubug.c
@@ -24,34 +24,12 @@
 #include <arch/io.h>
 #include <stdint.h>
 #include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>
-#include <cpu/amd/lxdef.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-
-
-#if 0
-void
-bug645(void){
-	msr_t msr;
-	rdmsr(CPU_ID_CONFIG);
-	msr.whatever |= ID_CONFIG_SERIAL_SET;
-	wrmsr(msr);
-}
-
-void
-bug573(void){
-	msr_t msr;
+#include <cpu/amd/lxdef.h>
 
-	msr = rdmsr(MC_GLD_MSR_PM);
-	msr.eax &= 0xfff3;
-	wrmsr(MC_GLD_MSR_PM);
-}
-#endif
 
 /**************************************************************************
  *
@@ -61,14 +39,8 @@ bug573(void){
  *	PCI cache deadlock
  *	There is also fix code in cache and PCI functions. This bug is very is pervasive.
  *
- *	Entry:
- *	Exit:
- *	Modified:
- *
  **************************************************************************/
-static void
-pcideadlock(void)
-{
+static void pcideadlock(void){
 	msr_t msr;
 
 	/*
@@ -77,18 +49,9 @@ pcideadlock(void)
 	 * for PCI writes to complete.
 	*/
 	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
-	msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
 	msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
 	wrmsr(CPU_DM_CONFIG0, msr);
 
-	/* interlock instruction fetches to WS regions with data accesses.
-	 * This prevents an instruction fetch from going out to PCI if the 
-	 * data side is about to make a request.
-	 */
-	msr = rdmsr(CPU_IM_CONFIG);
-	msr.lo |= IM_CONFIG_LOWER_QWT_SET;
-	wrmsr(CPU_IM_CONFIG, msr);
 	
 	/* write serialize memory hole to PCI. Need to unWS when something is 
 	 * shadowed regardless of cachablility.
@@ -100,249 +63,6 @@ pcideadlock(void)
 	wrmsr( CPU_RCONF_E0_FF, msr);
 }
 
-/**************************************************************************** 
- *
- *	CPUbug784
- *
- *	Bugtool #784 + #792
- *
- *	Fix CPUID instructions for < 3.0 CPUs
- *
- *	Entry:
- *	Exit:
- *	Modified:
- *
- ****************************************************************************/
-
-void bug784(void)
-{
-	msr_t msr;
-	//static char *name = "Geode by NSC";
-
-	/* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
-	 * would do this -- the OS can figure this type of stuff out!
-	 */
-	msr = rdmsr(0x3006);
-	msr.hi = 0x646f6547;
-	wrmsr(0x3006, msr);
-
-	msr = rdmsr(0x3007);
-	msr.hi = 0x79622065;
-	msr.lo = 0x43534e20;
-	wrmsr(0x3007, msr);
-
-	msr = rdmsr(0x3002);
-	wrmsr(0x3008, msr);
-
-	/* More CPUID to match AMD better. #792*/
-	msr = rdmsr(0x3009);
-	msr.hi = 0x0C0C0A13D;
-	msr.lo = 0x00000000;
-	wrmsr(0x3009, msr);
-}
-
-/* cpubug 1398: enable MC if we KNOW we have DDR*/
-/**************************************************************************
- *
- *	CPUbugIAENG1398
- *
- *	ClearQuest #IAENG1398
- *	The MC can not be enabled with SDR memory but can for DDR. Enable for
- *	DDR here if the setup token is "Default"
- *	Add this back to core by default once 2.0 CPUs are not supported.
- *	Entry:
- *	Exit:
- *	Modified:
- *
- **************************************************************************/
-void eng1398(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(MSR_GLCP+0x17);
-	if ((msr.lo & 0xff) <= CPU_REV_2_0) {
-		msr = rdmsr(GLCP_SYS_RSTPLL);
-		if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
-			return;
-	}
-
-	/* no CMOS/NVRAM to check, so enable MC Clock Gating */
-	msr = rdmsr(MC_GLD_MSR_PM);
-	msr.lo |= 3; /* enable MC clock gating.*/
-	wrmsr(MC_GLD_MSR_PM, msr);
-}
-
-/***************************************************************************
- *
- *	CPUbugIAENG2900
- *
- *	Clear Quest IAENG00002900, VSS 118.150
- *
- *	BTB issue causes blue screen in windows, but the fix is required
- *	for all operating systems.
- *
- *	Entry:
- *	Exit:
- *	Modified:
- *
- **************************************************************************/
-void
-eng2900(void)
-{
-	msr_t msr;
-
-	printk_debug("CPU_BUG:%s\n", __FUNCTION__);
-	/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
-	msr = rdmsr(0x3003);
-	msr.hi &= 0xFFFFF7FF;
-	wrmsr(0x3003, msr);
-
-	/* change this value to zero if you need to disable this BTB SWAPSiF. */
-	if (1) { 
-
-		/* Disable enable_actions in DIAGCTL while setting up GLCP */
-		msr.hi = 0;
-		msr.lo = 0;
-		wrmsr(MSR_GLCP + 0x005f, msr);
-
-		/* Changing DBGCLKCTL register to GeodeLink */
-		msr.hi = 0;
-		msr.lo = 0;
-		wrmsr(MSR_GLCP + 0x0016, msr);
-
-		msr.hi = 0;
-		msr.lo = 2;
-		wrmsr(MSR_GLCP + 0x0016, msr);
-
-		/* The code below sets up the CPU to stall for 4 GeodeLink 
-		 * clocks when CPU is snooped.  Because setting XSTATE to 0 
-		 * overrides any other XSTATE action, the code will always 
-		 * stall for 4 GeodeLink clocks after a snoop request goes 
-		 * away even if it occured a clock or two later than a 
-		 * different snoop; the stall signal will never 'glitch high' 
-		 * for only one or two CPU clocks with this code.
-		 */
-
-		/* Send mb0 port 3 requests to upper GeodeLink diag bits 
-		   [63:32] */
-		msr.hi = 0;
-		msr.lo = 0x80338041;
-		wrmsr(MSR_GLIU0 + 0x2005, msr);
-
-		/* set5m watches request ready from mb0 to CPU (snoop) */
-		msr.hi = 0x5ad68000;
-		msr.lo = 0;
-		wrmsr(MSR_GLCP + 0x0045, msr);
-
-		/* SET4M will be high when state is idle (XSTATE=11) */
-		msr.hi = 0;
-		msr.lo = 0x0140;
-		wrmsr(MSR_GLCP + 0x0044, msr);
-
-		/* SET5n to watch for processor stalled state */
-		msr.hi = 0x2000;
-		msr.lo = 0;
-		wrmsr(MSR_GLCP + 0x004D, msr);
-
-		/* Writing action number 13: XSTATE=0 to occur when CPU is 
-		   snooped unless we're stalled */
-		msr.hi = 0;
-		msr.lo = 0x00400000;
-		wrmsr(MSR_GLCP + 0x0075, msr);
-
-		/* Writing action number 11: inc XSTATE every GeodeLink clock 
-		   unless we're idle */
-		msr.hi = 0;
-		msr.lo = 0x30000;
-		wrmsr(MSR_GLCP + 0x0073, msr);
-
-		/* Writing action number 5: STALL_CPU_PIPE when exitting idle 
-		   state or not in idle state */
-		msr.hi = 0;
-		msr.lo = 0x00430000;
-		wrmsr(MSR_GLCP + 0x006D, msr);
-
-		/* Writing DIAGCTL Register to enable the stall action and to 
-		   let set5m watch the upper GeodeLink diag bits. */
-		msr.hi = 0;
-		msr.lo = 0x80004000;
-		wrmsr(MSR_GLCP + 0x005f, msr);
-	}
-}
-
-void bug118253(void)
-{
-	/* GLPCI PIO Post Control shouldn't be enabled */
-	msr_t msr;
-
-	msr = rdmsr(GLPCI_SPARE);
-	msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
-	wrmsr(GLPCI_SPARE, msr);
-}
-
-void bug118339(void)
-{
-	/* per AMD, do this always */
-	msr_t msr = {0,0};
-	int msrnum;
-
-	/* Disable enable_actions in DIAGCTL while setting up GLCP */
-	wrmsr(MSR_GLCP + 0x005f, msr);
-
-	/*  SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
-	msrnum =  MSR_GLCP + 0x042;
-	/* 	msr.hi =  2d6b8000h */;
-	msr.hi =  0x596b8000;
-	msr.lo =  0x00000a00;
-	wrmsr(msrnum, msr);
-
-	/*  SET3M fires if MBUS changed and VG pri is odd */
-	msrnum =  MSR_GLCP + 0x043;
-	msr.hi =  0x596b8040;
-	msr.lo = 0;
-	wrmsr(msrnum, msr);
-
-	/*  Put VG request data on lower diag bus */
-	msrnum =  MSR_GLIU0 + 0x2005;
-	msr.hi = 0;
-	msr.lo =  0x80338041;
-	wrmsr(msrnum, msr);
-
-	/*  Increment Y state if SET3M if true */
-	msrnum =  MSR_GLCP + 0x074;
-	msr.hi = 0;
-	msr.lo =  0x0000c000;
-	wrmsr(msrnum, msr);
-
-	/*  Set up MBUS action to PRI=3 read of MBIU */
-	msrnum =  MSR_GLCP + 0x020;
-	msr.hi =  0x0000d863;
-	msr.lo =  0x20002000;
-	wrmsr(msrnum, msr);
-
-	/*  Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
-	msrnum =  MSR_GLCP + 0x071;
-	msr.hi = 0;
-	msr.lo =  0x00000c00;
-	wrmsr(msrnum, msr);
-
-	/* Writing DIAGCTL */
-	msrnum =  MSR_GLCP + 0x005f;
-	msr.hi = 0;
-	msr.lo =  0x80004000;
-	wrmsr(msrnum, msr);
-
-	/*  Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
-	/*  As per Todd Roberts in PBz1094 and PBz1095 */
-	/*  Moved from CPUREG to CPUBUG per Tom Sylla */
-	msrnum =  0x04C000042;		/*  GLCP SETMCTL Register */;
-	msr = rdmsr(msrnum);
-	msr.hi |= 8;			/*  Bit 35 = MCP_IN */
-	wrmsr(msrnum, msr);
-}
-
-
-
 /****************************************************************************/
 /***/
 /**	DisableMemoryReorder*/
@@ -353,62 +73,18 @@ void bug118339(void)
 /**	 This is safe to do here and not in MC init since there is nothing*/
 /**	 to maintain coherency with and the cache is not enabled yet.*/
 /***/
-/***/
-/**	Entry:*/
-/**	Exit:*/
-/**	Modified:*/
-/***/
 /****************************************************************************/
-void disablememoryreadorder(void)
-{	
+static void disablememoryreadorder(void){
 	msr_t msr;
-	msr = rdmsr(MC_CF8F_DATA);
 
+	msr = rdmsr(MC_CF8F_DATA);
 	msr.hi |=  CF8F_UPPER_REORDER_DIS_SET;
 	wrmsr(MC_CF8F_DATA, msr);
 }
 
-void
-cpubug(void)
-{
-#if 0 //GX3: any CPU bugs to fix here? :)
-	msr_t msr;
-	int rev;
-
-	msr = rdmsr(GLCP_CHIP_REVID);
-
-	rev = msr.lo & 0xff;
-	if (rev < 0x20) {
-		printk_err("%s: rev < 0x20! bailing!\n");
-		return;
-	}
-	printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
-	switch(rev)
-	{
-		case 0x20:
+/* For cpu version C3. Should be the only released version */
+void cpubug(void) {
 			pcideadlock();
-			eng1398();
-			/* cs 5530 bug; ignore 
-			bug752();
-			*/
-			break;
-		case 0x21:
-			pcideadlock();
-			eng1398();
-			eng2900();
-			bug118339();
-			break;
-		case 0x22:
-		case 0x30: 
-			break;
-		default:
-			printk_err("unknown rev %x, bailing\n", rev);
-			return;
-	}
-	bug784();
-	bug118253();
 	disablememoryreadorder();
 	printk_debug("Done cpubug fixes \n");
-#endif
-
 }
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index e8ccb13bbb..4607e3dea4 100644
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -20,77 +20,219 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* ***************************************************************************/
-/* **/
-/* *	BIST */
-/* **/
-/* *	GX2 BISTs need to be run before BTB or caches are enabled.*/
-/* *	BIST result left in registers on failure to be checked with FS2.*/
-/* **/
-/* ***************************************************************************/
-static void
-BIST(void){
-	int msrnum;
+/**************************************************************************
+;*
+;*	SetDelayControl
+;*
+;*************************************************************************/
+void SetDelayControl(void){
+	unsigned int msrnum, glspeed;
+	unsigned char spdbyte0, spdbyte1;
 	msr_t msr;
 
-	/* DM*/
-	msrnum = CPU_DM_CONFIG0;
-	msr = rdmsr(msrnum);
-	msr.lo |=  DM_CONFIG0_LOWER_DCDIS_SET;
+	glspeed = GeodeLinkSpeed();
+
+	/* fix delay controls for DM and IM arrays */
+	msrnum = CPU_BC_MSS_ARRAY_CTL0;
+	msr.hi = 0;
+	msr.lo = 0x2814D352;
 	wrmsr(msrnum, msr);
 	
-	msr.lo =  0x00000003F;
-	msr.hi =  0x000000000;
-	msrnum = CPU_DM_BIST;
+	msrnum = CPU_BC_MSS_ARRAY_CTL1;
+	msr.hi = 0;
+	msr.lo = 0x1068334D;
 	wrmsr(msrnum, msr);
 
-	outb(POST_CPU_DM_BIST_FAILURE, 0x80);				/* 0x29*/
-	msr = rdmsr(msrnum);						/* read back for pass fail*/
-	msr.lo &= 0x0F3FF0000;
-	if (msr.lo != 0xfeff0000)
-		goto BISTFail;
+	msrnum = CPU_BC_MSS_ARRAY_CTL2;
+	msr.hi = 0x00000106;
+	msr.lo = 0x83104104;
+	wrmsr(msrnum,msr);
  
-	msrnum = CPU_DM_CONFIG0;
+	msrnum = GLCP_FIFOCTL;
 	msr = rdmsr(msrnum);
-	msr.lo &=  ~ DM_CONFIG0_LOWER_DCDIS_SET;
+	msr.hi = 0x00000005;
 	wrmsr(msrnum, msr);
 
-	/* FPU*/
-	msr.lo =  0x000000131;
+	/* Enable setting */
+	msrnum = CPU_BC_MSS_ARRAY_CTL_ENA;
 	msr.hi = 0;
-	msrnum = CPU_FP_UROM_BIST;
+	msr.lo = 0x00000001;
 	wrmsr(msrnum, msr);
 
-	outb(POST_CPU_FPU_BIST_FAILURE, 0x80);				/* 0x89*/
-	inb(0x80);									/*  IO delay*/
-	msr = rdmsr(msrnum);							/* read back for pass fail*/
-	while ((msr.lo&0x884) != 0x884)
-		msr = rdmsr(msrnum);					/*  Endless loop if BIST is broken*/
-	if ((msr.lo&0x642) != 0x642)
-		goto BISTFail;
 
-	msr.lo = msr.hi = 0;				/*  clear FPU BIST bits*/
-	msrnum = CPU_FP_UROM_BIST;
-	wrmsr(msrnum, msr);
+	/* Debug Delay Control Setup Check
+	Leave it alone if it has been setup. FS2 or something is here.*/
+	msrnum = GLCP_DELAY_CONTROLS;
+	msr = rdmsr(msrnum);
+	if (msr.lo & ~(0x7C0)){
+		return;
+	}
 
 
-	/* BTB*/
-	msr.lo =  0x000000303;
-	msr.hi =  0x000000000;
-	msrnum = CPU_PF_BTBRMA_BIST;
-	wrmsr(msrnum, msr);
+	/*
+	; Delay Controls based on DIMM loading. UGH!
+	; # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
+	; Note - We only support module width of 64.
+	*/
+	spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
+	if (spdbyte0 !=0xFF){
+		spdbyte0 = (unsigned char) 64/spdbyte0 * (unsigned char) (spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS));
+	}
+	else{
+		spdbyte0=0;
+	}
+
+	spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH);
+	if (spdbyte1 !=0xFF){
+		spdbyte1 = (unsigned char) 64/spdbyte1 * (unsigned char) (spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS));
+	}
+	else{
+		spdbyte1=0;
+	}
 
-	outb(POST_CPU_BTB_BIST_FAILURE	, 0x80);				/* 0x8A*/
-	msr = rdmsr(msrnum);							/* read back for pass fail*/
-	if ((msr.lo & 0x3030) != 0x3030)
-		goto BISTFail;
 
-	return;
 
-BISTFail:
-	print_err("BIST failed!\n");
-	while(1);
+/* The current thinking. Subject to change...
+
+;								   "FUTURE ROBUSTNESS" PROPOSAL
+;								   ----------------------------
+;		DIMM	 Max MBUS					   MC 0x2000001A bits 26:24
+;DIMMs	devices	 Frequency	 MCP 0x4C00000F Setting		 vvv
+;-----	-------	 ---------	 ----------------------	 ----------
+;1		 4		 400MHz		 0x82*100FF 0x56960004		  4
+;1		 8		 400MHz		 0x82*100AA 0x56960004		  4
+;1		 16		 400MHz		 0x82*10055 0x56960004		  4
+;
+;2		 4,4	 400MHz		 0x82710000 0x56960004		  4
+;2		 8,8	 400MHz		 0xC27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
+;
+;2		16,4	 >333		 0xB27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
+;2		16,8	 >333		 0xB27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
+;2		16,16	 >333		 0xB2710000 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
+;
+;1		 4		 <=333MHz	 0x83*100FF 0x56960004		  3
+;1		 8		 <=333MHz	 0x83*100AA 0x56960004		  3
+;1		 16		 <=333MHz	 0x83*100AA 0x56960004		  3
+;
+;2		 4,4	 <=333MHz	 0x837100A5 0x56960004		  3
+;2		 8,8	 <=333MHz	 0x937100A5 0x56960004		  3
+;
+;2		16,4	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
+;2		16,8	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
+;2		16,16	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
+;=========================================================================
+;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
+;	 but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
+;	 Bits 54:52 should always be set to '111'.
+
+;No VTT termination
+;-------------------------------------
+;ADDR/CTL have 22 ohm series R
+;DQ/DQM/DQS have 33 ohm series R
+;
+;		DIMM	 Max MBUS
+;DIMMs	devices	 Frequency	 MCP 0x4C00000F Setting
+;-----	-------	 ---------	 ----------------------
+;1		 4		 400MHz		 0xF2F100FF 0x56960004		  4			The MC changes improve Salsa.
+;1		 8		 400MHz		 0xF2F100FF 0x56960004		  4			Delay controls no real change,
+;1		 4		 <=333MHz	 0xF2F100FF 0x56960004		  3			just fixing typo in left side.
+;1		 8		 <=333MHz	 0xF2F100FF 0x56960004		  3
+;1		 16		 <=333MHz	 0xF2F100FF 0x56960004		  3
+*/
+	msr.hi = msr.lo = 0;
+
+	if (spdbyte0 == 0 || spdbyte1 == 0){
+		/* one dimm solution */
+		if (spdbyte1 == 0){
+			msr.hi |= 0x000800000;
+		}
+		spdbyte0 += spdbyte1;
+		if (spdbyte0 > 8){
+			/* large dimm */
+			if (glspeed < 334){
+				msr.hi |= 0x0837100AA;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x082710055;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else if (spdbyte0 > 4){
+			/* medium dimm */
+			if (glspeed < 334){
+				msr.hi |= 0x0837100AA;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0827100AA;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else{
+			/* small dimm */
+			if (glspeed < 334){
+				msr.hi |= 0x0837100FF;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0827100FF;
+				msr.lo |= 0x056960004;
+			}
+		}
+	}
+	else{
+		/* two dimm solution */
+		spdbyte0 += spdbyte1;
+		if (spdbyte0 > 24){
+			/* huge dimms */
+			if (glspeed < 334){
+				msr.hi |= 0x0B37100A5;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0B2710000;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else if (spdbyte0 > 16){
+			/* large dimms */
+			if (glspeed < 334){
+				msr.hi |= 0x0B37100A5;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0B27100A5;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else if (spdbyte0 >= 8){
+			/* medium dimms */
+			if (glspeed < 334){
+				msr.hi |= 0x0937100A5;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0C27100A5;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else{
+			/* small dimms */
+			if (glspeed < 334){
+				msr.hi |= 0x0837100A5;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x082710000;
+				msr.lo |= 0x056960004;
+			}
+		}
+	}
+	wrmsr(GLCP_DELAY_CONTROLS,msr);
+	return;
 }
+
 /* ***************************************************************************/
 /* *	cpuRegInit*/
 /* ***************************************************************************/
@@ -99,173 +241,78 @@ cpuRegInit (void){
 	int msrnum;
 	msr_t msr;
 	
-	//GX3 suspend: what is desired?
-
-	/*  Enable Suspend on Halt*/
-	/*msrnum = CPU_XC_CONFIG;
+	/* Castle 2.0 BTM periodic sync period. */
+	/*	[40:37] 1 sync record per 256 bytes */
+	msrnum = CPU_PF_CONF;
 	msr = rdmsr(msrnum);
-	msr.lo |=  XC_CONFIG_SUSP_ON_HLT;
-	wrmsr(msrnum, msr);*/
-
-	/*  ENable SUSP and allow TSC to run in Suspend */
-	/*  to keep speed detection happy*/
-	/*msrnum = CPU_BC_CONF_0;
-	msr = rdmsr(msrnum);
-	msr.lo |=  TSC_SUSP_SET | SUSP_EN_SET;
-	wrmsr(msrnum, msr);*/
-
-	/*  Setup throttling to proper mode if it is ever enabled.*/
-	msrnum = 0x04C00001E;
-	msr.hi =  0x000000000;
-	msr.lo =  0x00000603C;
-	wrmsr(msrnum, msr);		// GX3 OK +/-
-
+	msr.hi |= (0x8 << 5);
+	wrmsr(msrnum, msr);
 
-/*  Only do this if we are building for 5535*/
-/* */
-/*  FooGlue Setup*/
-/* */
-#if 0
-	/*  Enable CIS mode B in FooGlue*/
-	msrnum = MSR_FG + 0x10;
+	/*
+	; Castle performance setting.
+	; Enable Quack for fewer re-RAS on the MC
+	*/
+	msrnum = GLIU0_ARB;
 	msr = rdmsr(msrnum);
-	msr.lo &= ~3;
-	msr.lo |= 2;			/*  ModeB*/
+	msr.hi &= ~ARB_UPPER_DACK_EN_SET;
+	msr.hi |= ARB_UPPER_QUACK_EN_SET;
 	wrmsr(msrnum, msr);
-#endif
-
-/* */
-/*  Disable DOT PLL. Graphics init will enable it if needed.*/
-/* */
-
-// GX3: Disable DOT PLL? No. Lets tick.
 
-/*	msrnum = GLCP_DOTPLL;
+	msrnum = GLIU1_ARB;
 	msr = rdmsr(msrnum);
-	msr.lo |= DOTPPL_LOWER_PD_SET;
-	wrmsr(msrnum, msr); */
+	msr.hi &= ~ARB_UPPER_DACK_EN_SET;
+	msr.hi |= ARB_UPPER_QUACK_EN_SET;
+	wrmsr(msrnum, msr);
 
-/* */
-/*  Enable RSDC*/
-/* */
-	msrnum = 0x1301 ;
+	/*	GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
+	msrnum = GLIU1_PORT_ACTIVE;
 	msr = rdmsr(msrnum);
-	msr.lo |=  0x08;
-	wrmsr(msrnum, msr);		//GX3 OK
-
-
-/* */
-/*  BIST*/
-/* */
-	/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
-	{
-//		BIST();
-	}
-
-
-/* */
-/*  Enable BTB*/
-/* */
-	/*  I hate to put this check here but it doesn't really work in cpubug.asm*/
+	msr.lo &= ~0x880;
+	wrmsr(msrnum, msr);
 
-//GX3: BTB is enabled by default
+	/* Set the Delay Control in GLCP */
+	SetDelayControl();
 
-/*	msrnum = MSR_GLCP+0x17;
+/*  Enable RSDC*/
+	msrnum = CPU_AC_SMM_CTL;
 	msr = rdmsr(msrnum);
-	if (msr.lo >= CPU_REV_2_1){
-		msrnum = CPU_PF_BTB_CONF;
-		msr = rdmsr(msrnum);
-		msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
+	msr.lo |= SMM_INST_EN_SET;
 		wrmsr(msrnum, msr);
-	}
-
-	*/
 
-/* */
-/*  FPU impercise exceptions bit*/
-/* */
-	/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
 
-
-
-// GX3: FPU impercise exceptions bit - what's that?
-/*	{
+	/* FPU imprecise exceptions bit */
 		msrnum = CPU_FPU_MSR_MODE;
 		msr = rdmsr(msrnum);
 		msr.lo |= FPU_IE_SET;
 		wrmsr(msrnum, msr);
-	}
-
-	*/
 
-#if 0
-	/* */
-	/*  Cache Overides*/
-	/* */
-	/* This code disables the data cache.  Don't execute this
-	 * unless you're testing something.
-	 */ 
-	/*  Allow NVRam to override DM Setup*/
-	/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
-	{
 
-		msrnum = CPU_DM_CONFIG0;
+	/* Power Savers (Do after BIST) */
+	/* Enable Suspend on HLT & PAUSE instructions*/
+	msrnum = CPU_XC_CONFIG;
 		msr = rdmsr(msrnum);
-		msr.lo |=  DM_CONFIG0_LOWER_DCDIS_SET;
+	msr.lo |= XC_CONFIG_SUSP_ON_HLT |  XC_CONFIG_SUSP_ON_PAUSE;
 		wrmsr(msrnum, msr);
-	}
-	/* This code disables the instruction cache.  Don't execute
-	 * this unless you're testing something.
-	*/ 
-	/*  Allow NVRam to override IM Setup*/
-	/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
-	{
-		msrnum = CPU_IM_CONFIG;
+
+	/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
+	msrnum = CPU_BC_CONF_0;
 		msr = rdmsr(msrnum);
-		msr.lo |=  IM_CONFIG_LOWER_ICD_SET;
+	msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
+	msr.lo &= 0x0F0FFFFFF;
+	msr.lo |= 0x002000000;	 /* PBZ213: Set PAUSEDLY = 2 */
 		wrmsr(msrnum, msr);
-	}
-#endif
-}
 
-
-
-
-/* ***************************************************************************/
-/* **/
-/* *	MTestPinCheckBX*/
-/* **/
-/* *	Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/
-/* *  This version is called when there isn't a stack available*/
-/* **/
-/* ***************************************************************************/
-static void
-MTestPinCheckBX (void){
-	int msrnum;
-	msr_t msr;
-
-	/*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/
-			/* return ; */
-	/* } */
-
-	/*  Turn on MTEST*/
-	msrnum = MC_CFCLK_DBUG;
-	msr = rdmsr(msrnum);
-	msr.hi |=  CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET;
+	/* Disable the debug clock to save power.*/
+	/* NOTE: leave it enabled for fs2 debug */
+/*	msrnum = GLCP_DBGCLKCTL;
+	msr.hi = 0;
+	msr.lo = 0;
 	wrmsr(msrnum, msr);
+*/
 
-	msrnum = GLCP_SYS_RSTPLL			/*  Get SDR/DDR mode from GLCP*/;
-	msr = rdmsr(msrnum);
-	msr.lo >>=  RSTPPL_LOWER_SDRMODE_SHIFT;
-	if (msr.lo & 1) {
-		msrnum = MC_CFCLK_DBUG;			/*  Turn on SDR MTEST stuff*/
-		msr = rdmsr(msrnum);
-		msr.lo |=  CFCLK_LOWER_SDCLK_SET;
-		msr.hi |=  CFCLK_UPPER_MTST_DQS_EN_SET;
+	/* Setup throttling delays to proper mode if it is ever enabled. */
+	msrnum = GLCP_TH_OD;
+	msr.hi = 0;
+	msr.lo = 0x00000603C;
 		wrmsr(msrnum, msr);
 	}
-
-	/*  Lock the cache down here.*/
-	__asm__("wbinvd\n");
-
-}
diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c
index 541b3649ce..1cdfda8e54 100644
--- a/src/cpu/amd/model_lx/model_lx_init.c
+++ b/src/cpu/amd/model_lx/model_lx_init.c
@@ -46,7 +46,6 @@ static void model_lx_init(device_t dev)
 	printk_debug("model_lx_init\n");
 
 	/* Turn on caching if we haven't already */
-	
 	x86_enable_cache();
 
 	/* Enable the local cpu apics */
@@ -60,7 +59,7 @@ static void model_lx_init(device_t dev)
 	outb(0x02,0x92);
 	printk_debug("A20 (0x92): %d\n",inb(0x92));
 
-	printk_debug("model_lx_init DONE\n");
+	printk_debug("CPU model_lx_init DONE\n");
 };
 
 static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c
index d2e4cf11da..4bc362c52c 100644
--- a/src/cpu/amd/model_lx/syspreinit.c
+++ b/src/cpu/amd/model_lx/syspreinit.c
@@ -21,8 +21,6 @@
  */
 
 /* ***************************************************************************/
-
-/* ***************************************************************************/
 /* **/
 /* *	StartTimer1*/
 /* **/
@@ -41,6 +39,8 @@ void
 SystemPreInit(void){
 
 	/* they want a jump ... */
-	__asm__("jmp .+2\ninvd\njmp.+2\n");
+#ifndef USE_DCACHE_RAM
+	__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
+#endif
 	StartTimer1();
 }
diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c
index 0a5f792b49..e2922e1859 100644
--- a/src/cpu/amd/model_lx/vsmsetup.c
+++ b/src/cpu/amd/model_lx/vsmsetup.c
@@ -69,6 +69,9 @@
  *  software, even if advised of the possibility of such damage.
  *
  *  $Id: vsmsetup.c,v 1.8 2006/09/08 12:47:57 andrei Exp $
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
  *--------------------------------------------------------------------*/
 
 /* Modified to be a self sufficient plug in so that it can be used 
@@ -300,13 +303,13 @@ void do_vsmbios(void)
 	printk_err("do_vsmbios\n");
 	/* clear vsm bios data area */
 	for (i = 0x400; i < 0x500; i++) {
-		*(unsigned char *) i = 0;
+		*(volatile unsigned char *) i = 0;
 	}
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	/* this is the base of rom on the GX2 at present. At some point, this has to be 
+	/* this is the base of rom on the LX at present. At some point, this has to be
 	  * much better parameterized 
 	  */
 	//rom = 0xfff80000;
@@ -314,8 +317,10 @@ void do_vsmbios(void)
 	/* the VSA starts at the base of rom - 64 */
 	//rom = ((unsigned long) 0) - (ROM_SIZE  + 64*1024);
 	
-	rom = 0xfffc8000;
+	//rom = 0xfffc8000;
 
+	//VSA is cat onto the end after LB builds
+	rom = ((unsigned long) 0) - (ROM_SIZE + 36 * 1024);
 	buf = (unsigned char *) VSA2_BUFFER;
 	olen = unrv2b((uint8_t *)rom, buf, &ilen);
 	printk_debug("buf ilen %d olen%d\n", ilen, olen);