summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-10-12 14:35:25 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-10-28 11:59:17 +0000
commitbe9533aba957e9c43f77381f436906951c13c98b (patch)
treeb4ad42a54424f29043ce91b7d5135e6de2cad6f1 /src/cpu
parent942ad6a137027d6a7d8d082dee20bb64c81dc813 (diff)
downloadcoreboot-be9533aba957e9c43f77381f436906951c13c98b.tar.xz
nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support
The i82801ix_early_init is now called both in the bootblock and romstage. The rationale behind setting this up twice is to ensure bootblock-romstage compatibility in the future if for instance VBOOT is used. This moves the console init to the bootblock. The romstage now runs uncached. Adding a prog_run hooks to set up an MTRR to cache the romstage will be done in a followup patch. The default size of 64KiB is not modified for the bootblock as trying to fit both EHCI and SPI flash debugging needs a more space and 64KiB is the next power of 2 size that fits it. TESTED on Thinkpad X200. Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/socket_BGA956/Kconfig4
-rw-r--r--src/cpu/intel/socket_BGA956/Makefile.inc3
-rw-r--r--src/cpu/intel/socket_p/Kconfig4
-rw-r--r--src/cpu/intel/socket_p/Makefile.inc3
4 files changed, 12 insertions, 2 deletions
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index 6c5e414029..eef81d570a 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -14,4 +14,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
endif
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 05514a1548..7656416aad 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -8,7 +8,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+bootblock-y += ../car/core2/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig
index 0ec9ced5d0..6ba74eea90 100644
--- a/src/cpu/intel/socket_p/Kconfig
+++ b/src/cpu/intel/socket_p/Kconfig
@@ -15,4 +15,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
endif
diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc
index 78d7c0ee58..76c4127d4d 100644
--- a/src/cpu/intel/socket_p/Makefile.inc
+++ b/src/cpu/intel/socket_p/Makefile.inc
@@ -9,7 +9,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+bootblock-y += ../car/core2/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c