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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-27 23:42:58 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-27 23:42:58 +0000
commitd7294596218addf11feefb4cb2411eb7729b5b11 (patch)
treeb1982471230bd052036f2a3fcca51285d750688b /src/cpu
parent70a373315513244266024c3591dc9db103f7ace1 (diff)
downloadcoreboot-d7294596218addf11feefb4cb2411eb7729b5b11.tar.xz
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart VSRamp in step b of 2.4.1.7 BKDG to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/model_10xxx/fidvid.c22
1 files changed, 17 insertions, 5 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index b1a064a869..b8cb4b295d 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -66,6 +66,21 @@ static void enable_fid_change(u8 fid)
}
}
+static void setVSRamp(device_t dev) {
+ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime]
+ * If this field accepts 8 values between 10 and 500 us why
+ * does page 324 say "BIOS should set this field to 001b."
+ * (20 us) ?
+ * Shouldn't it depend on the voltage regulators, mainboard
+ * or something ?
+ */
+ u32 dword;
+ dword = pci_read_config32(dev, 0xd8);
+ dword &= VSRAMP_MASK;
+ dword |= VSRAMP_VALUE;
+ pci_write_config32(dev, 0xd8, dword);
+}
+
static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
{
u8 pviModeFlag;
@@ -179,11 +194,8 @@ static void prep_fid_change(void)
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
dev = NODE_PCI(i, 3);
- dword = pci_read_config32(dev, 0xd8);
- dword &= VSRAMP_MASK;
- dword |= VSRAMP_VALUE;
- pci_write_config32(dev, 0xd8, dword);
-
+ setVSRamp(dev);
+ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
/* Figure out the value for VsSlamTime and program it */
recalculateVsSlamTimeSettingOnCorePre(dev);