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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-17 22:39:29 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-18 20:59:12 +0100 |
| commit | de01136484c58d13457ccf1e42fdb2310f3cbe65 (patch) | |
| tree | 86a7e28d7249ab7e605319d92a21211aa467d598 /src/cpu | |
| parent | b17f4e8d26b34541cade48add2a213454008d3f1 (diff) | |
| download | coreboot-de01136484c58d13457ccf1e42fdb2310f3cbe65.tar.xz | |
intel post-car: Increase stacktop alignment
Align top of stack to 8 bytes, value documented as FSP1.1 requirement.
Also fix some cases of uintptr_t casted to unsigned long.
Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17461
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index f823c55b0c..48920b3968 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -69,15 +69,13 @@ static inline u32 *stack_push(u32 *stack, u32 value) * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_romstage_stack_after_car(void) { - uintptr_t top_of_stack; int num_mtrrs; u32 *slot; u32 mtrr_mask_upper; u32 top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = romstage_ram_stack_top() & ~3; - slot = (void *)top_of_stack; + slot = (void *)romstage_ram_stack_top(); num_mtrrs = 0; /* The upper bits of the MTRR mask need to set according to the number |