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authorStefan Reinauer <stepan@coreboot.org>2010-12-12 00:37:41 +0000
committerStefan Reinauer <stepan@openbios.org>2010-12-12 00:37:41 +0000
commitdfeb04d46323b412e940ae5c4d52814b18670aa1 (patch)
tree44782bd683979189f9c475f5638c06ef327e2592 /src/cpu
parent4041925039f3504481a9f2263ca96669fc597a4a (diff)
downloadcoreboot-dfeb04d46323b412e940ae5c4d52814b18670aa1.tar.xz
fix model 106cx
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/model_106cx/model_106cx_init.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 2e38e775a6..1199315c48 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -97,14 +97,16 @@ static void configure_c_states(void)
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
wrmsr(PMG_CST_CONFIG_CONTROL, msr);
- // set P_BLK address
- msr = rdmsr(PMG_IO_BASE_ADDR);
- msr.lo = (PMB0 + 4) | (PMB1 << 16);
+ /* Set Processor MWAIT IO BASE (P_BLK) */
+ msr.hi = 0;
+ // TODO Do we want PM1_BASE? Needs SMM?
+ //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
+ msr.lo = ((PMB0_BASE + 4) & 0xffff);
wrmsr(PMG_IO_BASE_ADDR, msr);
- // set C_LVL controls
- msr = rdmsr(PMG_IO_CAPTURE_ADDR);
- msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
+ /* set C_LVL controls */
+ msr.hi = 0;
+ msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
wrmsr(PMG_IO_CAPTURE_ADDR, msr);
}