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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-23 13:28:57 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-24 12:04:25 +0000 |
| commit | e751a101c08d540c59fc39def9681a0ee227d825 (patch) | |
| tree | 89443ef7d6e3f5d8318dd5b8b9ff35834fc1bc91 /src/cpu | |
| parent | b89c8bb13536abeb84bfaad28bbbd8ebfacb0137 (diff) | |
| download | coreboot-e751a101c08d540c59fc39def9681a0ee227d825.tar.xz | |
soc/intel/broadwell: Move romstage.c to Haswell
Broadwell no longer has CPU code.
Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 30 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 3c4db4f1c8..bfb501133c 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,4 +1,6 @@ ramstage-y += haswell_init.c + +romstage-y += romstage.c romstage-y += ../car/romstage.c ramstage-y += acpi.c diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c new file mode 100644 index 0000000000..3b11e93cab --- /dev/null +++ b/src/cpu/intel/haswell/romstage.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <cpu/intel/haswell/haswell.h> +#include <cpu/x86/msr.h> + +void set_max_freq(void) +{ + msr_t msr, perf_ctl, platform_info; + + /* Check for configurable TDP option */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + + if ((platform_info.hi >> 1) & 3) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + + perf_ctl.hi = 0; + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); +} |