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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-09-28 21:39:12 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-10-03 22:22:54 +0000
commitecf2eb463faff04ab6061eb5dfd8da26c5026a97 (patch)
tree4eca305b3d9e4b7d29caa664a1a1a923a06fa224 /src/cpu
parentac1f4b86f4a82f00c07aa21707703c5c70d9c604 (diff)
downloadcoreboot-ecf2eb463faff04ab6061eb5dfd8da26c5026a97.tar.xz
sandybridge ivybridge: Treat native init as first class citizen
This is a sad story. We have three different code paths for sandybridge and ivybridge: proper native path, google MRC path, and, everyone's favorite: Intel FSP path. For the purpose of this patch, the FSP path lives in its own little world, and doesn't concern us. Since MRC was first, when native files and variables were added, they were suffixed with "_native" to separate them from the existing code. This can cause confusion, as the suffix might make the native files seem parasitical. This has been bothering me for many months. MRC should be the parasitical path, especially since we fully support native init, and it works more reliably, on a wider range of hardware. There have been a few board ports that never made it to coreboot.org because MRC would hang. gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so the effort was abandoned at first. Once the native path became available, the effort was restarted and the board is now supported. In honor of the hackers and pioneers who made the native code possible, rename things so that their effort is the first class citizen. Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11788 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/Makefile.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 51451e90d0..859b73beab 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -17,10 +17,10 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B
subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += model_206ax
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax