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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-16 14:02:25 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-18 19:03:22 +0000
commit157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 (patch)
tree4562bd212e40d0832fa893935d85a06d82f8a897 /src/cpu
parent146c09823333c52e8bbca98465ccc8512ec1daa2 (diff)
downloadcoreboot-157b189f6b97b6e9ecd8d29edbbd045fbbc231f5.tar.xz
cpu/intel: Enter romstage without BIST
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/car/romstage.c2
-rw-r--r--src/cpu/intel/haswell/haswell.h1
-rw-r--r--src/cpu/intel/haswell/romstage.c6
3 files changed, 2 insertions, 7 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 43fbe8af38..28801458cd 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -61,7 +61,7 @@ static void romstage_main(unsigned long bist)
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
- mainboard_romstage_entry(bist);
+ mainboard_romstage_entry();
/* Check the stack. */
for (i = 0; i < num_guards; i++) {
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 819c2e44f3..4b5a3b094a 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -141,7 +141,6 @@ struct romstage_params {
struct pei_data *pei_data;
const void *gpio_map;
const struct rcba_config_instruction *rcba_config;
- unsigned long bist;
void (*copy_spd)(struct pei_data *);
};
void romstage_common(const struct romstage_params *params);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 544a93fd97..43f5109889 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -33,14 +33,10 @@ void romstage_common(const struct romstage_params *params)
int boot_mode;
int wake_from_s3;
- if (params->bist == 0)
- enable_lapic();
+ enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
- /* Halt if there was a built in self test failure */
- report_bist_failure(params->bist);
-
/* Perform some early chipset initialization required
* before RAM initialization can work
*/