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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-22 22:52:14 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-04-09 12:03:58 +0000
commit2c3fd499cf0672a8da669e40be84112a02b5a77c (patch)
treec2caa870a8923a4a87bfd3507029b0ddf6484114 /src/cpu
parentd538dd1fe70a333c929a2eb7c4106608bcd05257 (diff)
downloadcoreboot-2c3fd499cf0672a8da669e40be84112a02b5a77c.tar.xz
intel/nehalem post-car: Use postcar_frame for MTRR setup
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/model_2065x/cache_as_ram.inc63
1 files changed, 40 insertions, 23 deletions
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 33a7a6c57e..6cc995838e 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -170,8 +170,8 @@ before_romstage:
/* Call romstage.c main function. */
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down.
- */
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
movl %eax, %esp
post_code(0x30)
@@ -220,31 +220,48 @@ before_romstage:
post_code(0x38)
- /* Enable Write Back and Speculative Reads for the first MB
- * and ramstage.
- */
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
- movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
- xorl %edx, %edx
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
+
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
wrmsr
- movl $MTRR_PHYS_MASK(0), %ecx
- movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
- movl $CPU_PHYSMASK_HI, %edx // 36bit address space
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
wrmsr
+ inc %ecx
-#if CACHE_ROM_SIZE
- /* Enable Caching and speculative Reads for the
- * complete ROM now that we actually have RAM.
- */
- movl $MTRR_PHYS_BASE(1), %ecx
- movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRR_PHYS_MASK(1), %ecx
- movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-#endif
+ dec %ebx
+ jmp 2b
+2:
post_code(0x39)