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| author | Greg Watson <jarrah@users.sourceforge.net> | 2003-10-12 21:17:59 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2003-10-12 21:17:59 +0000 |
| commit | 2caf089187115a524c28d49fa5da3aae18c777e2 (patch) | |
| tree | eb65d9e16483d03cac34e4b18f82e3f9acbde7ed /src/cpu | |
| parent | fe78c82c40032285c3a8848c0444d7f3bf094446 (diff) | |
| download | coreboot-2caf089187115a524c28d49fa5da3aae18c777e2.tar.xz | |
naughty, naughty
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/ppc/ppc4xx/Config.lb | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb index 825450fd7f..0617c2a790 100644 --- a/src/cpu/ppc/ppc4xx/Config.lb +++ b/src/cpu/ppc/ppc4xx/Config.lb @@ -1,7 +1,23 @@ ## ## CPU initialization ## -initinclude "EARLY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc +uses _RAMBASE +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE + +## +## PPC4XX always uses cache ram for initial setup +## +option USE_DCACHE_RAM=1 +## Set dcache ram above linuxbios image +option DCACHE_RAM_BASE=_RAMBASE+0x100000 +## Dcache size is 16Kb +option DCACHE_RAM_SIZE=16384 + +initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc +initobject cache.S +initobject sdram.c object mem.o object clock.o |