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authorArthur Heymans <arthur@aheymans.xyz>2018-06-03 12:42:10 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-06-05 07:49:30 +0000
commit3a4edb6ea815fa24f02daeae9b80e6bde0871a9e (patch)
tree9b2ca36db034e16f22edf101dbcd2d5ea3acfb3a /src/cpu
parent4ff675ebd071755dcb278836a16ae1ea10c63e50 (diff)
downloadcoreboot-3a4edb6ea815fa24f02daeae9b80e6bde0871a9e.tar.xz
nb/intel/gm45: Switch to POSTCAR_STAGE
Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26788 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/socket_BGA956/Makefile.inc4
-rw-r--r--src/cpu/intel/socket_mPGA478MN/Makefile.inc4
2 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index f33b409c15..05514a1548 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -8,11 +8,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
-ifneq ($(CONFIG_POSTCAR_STAGE),y)
-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
-else
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S
-endif
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc
index ef89ac65a1..78d7c0ee58 100644
--- a/src/cpu/intel/socket_mPGA478MN/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc
@@ -9,11 +9,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
-ifneq ($(CONFIG_POSTCAR_STAGE),y)
-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
-else
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S
-endif
romstage-y += ../car/romstage.c