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authorStefan Reinauer <stepan@coresystems.de>2010-03-22 11:50:52 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-22 11:50:52 +0000
commit53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72 (patch)
tree1434912235e0ea29b20b4276ffbfce4f45e12dd5 /src/cpu
parentc02b4fc9db3c3c1e263027382697b566127f66bb (diff)
downloadcoreboot-53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72.tar.xz
drop some unused files and fix warnings on i945 based systems.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/Kconfig2
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram_disable.c6
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram_disable.c6
3 files changed, 8 insertions, 6 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 8d7c1a39c4..c336185705 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -10,11 +10,9 @@ config USE_DCACHE_RAM
config DCACHE_RAM_BASE
hex
- default 0xffdf8000 if CPU_INTEL_CORE
config DCACHE_RAM_SIZE
hex
- default 0x8000 if CPU_INTEL_CORE
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
index b9f7f669f9..fa7ab74bbc 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
@@ -19,6 +19,10 @@
#include "cpu/x86/car/copy_and_run.c"
+/* called from assembler code */
+void stage1_main(unsigned long bist);
+
+/* from romstage.c */
void real_main(unsigned long bist);
void stage1_main(unsigned long bist)
@@ -39,8 +43,6 @@ void stage1_main(unsigned long bist)
printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp);
}
-cpu_reset_x:
-
printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset);
if(cpu_reset == 0) {
diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
index 44ff264818..c21dd68e8d 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
@@ -21,6 +21,10 @@
#include "cpu/x86/car/copy_and_run.c"
+/* called from assembler code */
+void stage1_main(unsigned long bist);
+
+/* from romstage.c */
void real_main(unsigned long bist);
void stage1_main(unsigned long bist)
@@ -40,8 +44,6 @@ void stage1_main(unsigned long bist)
printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
#endif
-cpu_reset_x:
-
printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
printk(BIOS_SPEW, "No cache as ram now - ");