summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2018-07-03 14:59:50 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-08-13 15:38:38 +0000
commit65bb5434f6eb9e1f0f72a52958193b38057cfad7 (patch)
tree03700327ee52e7dc06fda83b5d193eca0cac7611 /src/cpu
parent870f69e2214d98a29e623a48953f305326e5870a (diff)
downloadcoreboot-65bb5434f6eb9e1f0f72a52958193b38057cfad7.tar.xz
src: Get rid of non-local header treated as local
Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c2
-rw-r--r--src/cpu/amd/family_10h-family_15h/model_10xxx_init.c2
-rw-r--r--src/cpu/intel/haswell/romstage.c10
3 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index a96811365a..75a0aba1e7 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -31,7 +31,7 @@
#include "cpu/amd/car/disable_cache_as_ram.c"
// For set_sysinfo_in_ram()
-#include "northbridge/amd/amdfam10/raminit.h"
+#include <northbridge/amd/amdfam10/raminit.h>
#if CONFIG_RAMTOP <= 0x100000
#error "You need to set CONFIG_RAMTOP greater than 1M"
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 58364d4cac..50406744bb 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -24,7 +24,7 @@
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdfam10/amdfam10.h"
+#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index b30d4af8b0..c74bfd6ff0 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -37,12 +37,12 @@
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#endif
-#include "haswell.h"
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
-#include "southbridge/intel/lynxpoint/me.h"
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/me.h>
#include <cpu/intel/romstage.h>
+#include "haswell.h"
static inline void reset_system(void)
{