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| author | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-09 15:56:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-11 20:51:33 +0100 |
| commit | 8cc846897132f6d6baa49118005815aefb5f560f (patch) | |
| tree | 113b69cccb4728084be3c5f83f04fe9f56db43e5 /src/cpu | |
| parent | 3b19cbae37ab340bd530e35412800a171733fda6 (diff) | |
| download | coreboot-8cc846897132f6d6baa49118005815aefb5f560f.tar.xz | |
Intel: Replace MSR 0xcd with MSR_FSB_FREQ
And move the corresponding #define to speedstep.h
Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2339
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_1067x/model_1067x_init.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/speedstep/acpi.c | 2 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/apic_timer.c | 5 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e81a6a7291..c821474446 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -99,7 +99,6 @@ static void enable_vmx(void) } #define MSR_BBL_CR_CTL3 0x11e -#define MSR_FSB_FREQ 0xcd static void configure_c_states(const int quad) { diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 910055d443..dfcc82e2da 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -67,7 +67,7 @@ static int determine_total_number_of_cores(void) */ static int get_fsb(void) { - const u32 fsbcode = rdmsr(0xcd).lo & 7; + const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; switch (fsbcode) { case 0: return 800; /* / 3 == 266 */ case 1: return 400; /* / 3 == 133 */ diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 53209fbbff..93e948fb0e 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -25,6 +25,7 @@ #include <cpu/x86/car.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/speedstep.h> /* NOTE: This code uses global variables, so it can not be used during * memory init. @@ -53,11 +54,11 @@ static int set_timer_fsb(void) switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; + timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; + timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ |