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authorArthur Heymans <arthur@aheymans.xyz>2018-01-25 00:33:45 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-07-30 19:11:00 +0000
commitaade90e68d26a90fbea0dccdaae3493bdf31829a (patch)
tree5e31d203c4beecb94250a458e67cc7d639f0b250 /src/cpu
parent6cd2c2f6ff792d1a170cd090e3347cfe2e14ac15 (diff)
downloadcoreboot-aade90e68d26a90fbea0dccdaae3493bdf31829a.tar.xz
nb/intel/gm45: Use common code for SMM in TSEG
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/model_1067x/Makefile.inc1
-rw-r--r--src/cpu/intel/model_6fx/Makefile.inc1
-rw-r--r--src/cpu/intel/smm/gen1/smi.h1
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c2
4 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index 3e6cb2c24b..133c9cff8f 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,5 +1,6 @@
ramstage-y += model_1067x_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index de6fd8d93d..a0824fdb18 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,5 +1,6 @@
ramstage-y += model_6fx_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index c328eae91a..f4cbbc3699 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -16,5 +16,6 @@ void southbridge_smm_init(void);
void southbridge_trigger_smi(void);
void southbridge_clear_smi_status(void);
u32 northbridge_get_tseg_base(void);
+u32 northbridge_get_tseg_size(void);
int cpu_get_apic_id_map(int *apic_id_map);
void northbridge_write_smram(u8 smram);
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index c50d8a4743..b48fe006bc 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -147,7 +147,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
/* TSEG base is usually aligned down (to 8MiB). So we can't
derive the TSEG size from the distance to GTT but use the
configuration value instead. */
- const u32 tseg_size = CONFIG_SMM_TSEG_SIZE;
+ const u32 tseg_size = northbridge_get_tseg_size();
/* The SMRAM available to the handler is 4MiB
since the IEDRAM lives at TSEGMB + 4MiB. */