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| author | Greg Watson <jarrah@users.sourceforge.net> | 2004-04-21 22:13:46 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2004-04-21 22:13:46 +0000 |
| commit | be167e79cf23bfc530c6973a7879a2451c28e422 (patch) | |
| tree | 067663eba5d8110dd086c086430811b56c362199 /src/cpu | |
| parent | f955af80d957f9435ceaa460fdb5282bb99f9fc8 (diff) | |
| download | coreboot-be167e79cf23bfc530c6973a7879a2451c28e422.tar.xz | |
i like ori better
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/ppc/ppc4xx/ppc4xx.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/ppc/ppc4xx/ppc4xx.inc b/src/cpu/ppc/ppc4xx/ppc4xx.inc index eea497734e..b6c072fdfd 100644 --- a/src/cpu/ppc/ppc4xx/ppc4xx.inc +++ b/src/cpu/ppc/ppc4xx/ppc4xx.inc @@ -89,7 +89,7 @@ */ lis r4,0x8000 - addi r4,r4,0x0001 + ori r4,r4,0x0001 mticcr r4 /* instruction cache enable */ isync @@ -102,7 +102,7 @@ */ lis r4, DCACHE_RAM_BASE@ha - addi r4, r4, DCACHE_RAM_BASE@l + ori r4, r4, DCACHE_RAM_BASE@l srwi r4, r4, 27 subfic r4, r4, 31 li r0, 1 |