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authorDavid Hendricks <dhendrix@chromium.org>2013-01-17 15:07:35 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-01-18 00:26:53 +0100
commitfba42a793a67d8910b4ab7fdfb386bcda9896d13 (patch)
tree44edd08ae28e4260ad1cdbad4cccb40be4f840ce /src/cpu
parent1c706dc85830a1d91c7ff7c99ac48efd8d085613 (diff)
downloadcoreboot-fba42a793a67d8910b4ab7fdfb386bcda9896d13.tar.xz
Snow bootblock (bloated/debug version)
This is the bloated Snow bootblock which includes: - SPI driver - UART, including requisite I2C, Maxim PMIC, and clock config code. - Adjustments for magic offsets (id section, stack pointer address) This is just a temporary solution until we have romstage loading. Once that happens, we'll rip out all but the code necessary for copying SPI ROM content into SRAM. Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/samsung/exynos5250/Kconfig2
-rw-r--r--src/cpu/samsung/exynos5250/bootblock.c26
2 files changed, 18 insertions, 10 deletions
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index 3d66c77440..206df9260b 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -45,7 +45,7 @@ config IRAM_TOP
config SYS_INIT_SP_ADDR
hex
- default 0x0204F800
+ default 0x02058000
config IRAM_STACK
hex
diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c
index 58d0919f02..0d65676bb5 100644
--- a/src/cpu/samsung/exynos5250/bootblock.c
+++ b/src/cpu/samsung/exynos5250/bootblock.c
@@ -17,16 +17,24 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#if 0
+/*
+ * Set/clear program flow prediction and return the previous state.
+ */
+static int config_branch_prediction(int set_cr_z)
+{
+ unsigned int cr;
+
+ /* System Control Register: 11th bit Z Branch prediction enable */
+ cr = get_cr();
+ set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
+
+ return cr & CR_Z;
+}
+#endif
+
void bootblock_cpu_init(void);
void bootblock_cpu_init(void)
{
- /*
- * FIXME: this is a stub for now. It should eventually copy
- * romstage data (and maybe more) from SPI to SRAM.
- */
-#if 0
- volatile unsigned long *addr = (unsigned long *)0x1004330c;
- *addr |= 0x100;
- while (1) ;
-#endif
+ /* FIXME: this is a stub for now */
}