buildsystem: Make CPU microcode updating more configurable

This patch aims to improve the microcode in CBFS handling that was
brought by the last patches from Stefan and the Chromium team.

Choices in Kconfig
  - 1) Generate microcode from tree (default)
  - 2) Include external microcode file
  - 3) Do not put microcode in CBFS

The idea is to give the user full control over including non-free
blobs in the final ROM image.

MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode
is handled by a special class, cpu_microcode, as such:

cpu_microcode-y += microcode_file.c

MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is
needed by intel microcode updating. Once all intel cpus are converted to
cbfs updating, this variable can go away.

These files are then compiled and assembled into a binary CBFS file.
The advantage of doing it this way versus the current method is that
  1) The rule is CPU-agnostic
  2) Gives user more control over if and how to include microcode blobs
  3) The rules for building the microcode binary are kept in
   src/cpu/Makefile.inc, and thus would not clobber the other makefiles,
   which are already overloaded and very difficult to navigate.

Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1245
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

7 files changed, 134 insertions, 25 deletions

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index baf686ea75..1ed721f7e0 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,10 +62,90 @@ config SSE2
 	  streaming SIMD instructions. Some parts of coreboot can be built
 	  with more efficient code if SSE2 instructions are available.
 
-config MICROCODE_IN_CBFS
-	bool "Look for microcode in CBFS"
+endif # ARCH_X86
+
+config CPU_MICROCODE_IN_CBFS
+	bool
 	default n
+
+choice
+	prompt "Include CPU microcode in CBFS"
+	default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS
+	default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS
+
+config CPU_MICROCODE_CBFS_GENERATE
+	bool "Generate from tree"
 	help
-	  Load microcode updates from CBFS instead of compiling them in.
+	  Select this option if you want microcode updates to be assembled when
+	  building coreboot and included in the final image as a separate CBFS
+	  file. Microcode will not be hard-coded into ramstage.
 
-endif # ARCH_X86
+	  The microcode file and may be removed from the ROM image at a later
+	  time with cbfstool, if desired.
+
+	  If unsure, select this option.
+
+config CPU_MICROCODE_CBFS_EXTERNAL
+	bool "Include external microcode file"
+	help
+	  Select this option if you want to include an external file containing
+	  the CPU microcode. This will be included as a separate file in CBFS.
+	  A word of caution: only select this option if you are sure the
+	  microcode that you have is newer than the microcode shipping with
+	  coreboot.
+
+	  The microcode file and may be removed from the ROM image at a later
+	  time with cbfstool, if desired.
+
+	  If unsure, select "Generate from tree"
+
+config CPU_MICROCODE_FILE
+	  string "Path and filename of CPU microcode"
+	  depends on CPU_MICROCODE_CBFS_EXTERNAL
+	  default "cpu_microcode.bin"
+	  help
+	    The path and filename of the file containing the CPU microcode.
+
+config CPU_MICROCODE_CBFS_NONE
+	bool "Do not include microcode updates"
+	help
+	  Select this option if you do not want CPU microcode included in CBFS.
+	  Note that for some CPUs, the microcode is hard-coded into the source
+	  tree and is not loaded from CBFS. In this case, microcode will still
+	  be updated. There is a push to move all microcode to CBFS, but this
+	  change is not implemented for all CPUs.
+
+	  This option currently applies to:
+	    - Intel SandyBridge/IvyBridge
+	    - VIA Nano
+
+	  Microcode may be added to the ROM image at a later time with cbfstool,
+	  if desired.
+
+	  If unsure, select "Generate from tree"
+
+	  The GOOD:
+	  Microcode updates intend to solve issues that have been discovered
+	  after CPU production. The expected effect is that systems work as
+	  intended with the updated microcode, but we have also seen cases where
+	  issues were solved by not applying microcode updates.
+
+	  The BAD:
+	  Note that some operating system include these same microcode patches,
+	  so you may need to also disable microcode updates in your operating
+	  system for this option to have an effect.
+
+	  The UGLY:
+	  A word of CAUTION: some CPUs depend on microcode updates to function
+	  correctly. Not updating the microcode may leave the CPU operating at
+	  less than optimal performance, or may cause outright hangups.
+	  There are CPUs where coreboot cannot properly initialize the CPU
+	  without microcode updates
+	  For example, if running with the factory microcode, some Intel
+	  SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
+	  will hang when changing the frequency.
+
+	  Make sure you have a way of flashing the ROM externally before
+	  selecting this option.
+
+endchoice
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 57273cf8c3..938a8dfef1 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -1,3 +1,40 @@
+################################################################################
+## Subdirectories
+################################################################################
 subdirs-y += amd
 subdirs-y += intel
 subdirs-y += via
+
+################################################################################
+## Rules for building the microcode blob in CBFS
+################################################################################
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y)
+
+cbfs-files-y += cpu_microcode_blob.bin
+
+cpu_microcode_blob.bin-type = 0x53
+
+# External microcode file, or are we generating one ?
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
+cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
+else
+cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin
+endif
+
+# In case we have more than one "source" (cough) files containing microcode, we
+# Link them together in one large blob, so that we get all the microcode updates
+# in one file. This makes it easier for objcopy in the final step.
+# The --entry=0 is just here to suppress the LD warning. It does not affect the
+# final microcode file.
+$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
+	@printf "    LD         $(subst $(obj)/,,$(@))\n"
+	$(LD) -static --entry=0 $< -o $@
+
+# We have a lot of useless data in the large blob, and we are only interested in
+# the data section, so we only copy that part to the final microcode file
+$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+	@printf "  MICROCODE    $(subst $(obj)/,,$(@))\n"
+	$(OBJCOPY) -j .data -O binary $< $@
+
+endif
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index f4d01020d1..22655c9532 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1,15 +1,5 @@
-ramstage-y += microcode.c
-
-
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-
-SRC_PATH = src/cpu/intel/microcode
-FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
-$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c
-	$(CC) $(FLAGS) -MMD -c -o $@ $<
-
-$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o
-	objcopy -j .data -O binary $< $@
-
--include $(obj)/microcode_blob.d
-endif
+################################################################################
+## One small file with the awesome super-power of updating the cpu microcode
+## directly from CBFS. You have been WARNED!!!
+################################################################################
+ramstage-y += microcode.c
\ No newline at end of file
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index e84bad9beb..a4471ca042 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -28,7 +28,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
 
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
 #ifdef __PRE_RAM__
 #include <arch/cbfs.h>
 #else
@@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void)
 	return msr.hi;
 }
 
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
 static
 #endif
 void intel_update_microcode(const void *microcode_updates)
@@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates)
 	}
 }
 
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
 
-#define MICROCODE_CBFS_FILE "microcode_blob.bin"
+#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
 
 void intel_update_microcode_from_cbfs(void)
 {
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 6635868453..5c543b88ba 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SSE2
 	select UDELAY_LAPIC
 	select SMM_TSEG
-	select MICROCODE_IN_CBFS
+	select CPU_MICROCODE_IN_CBFS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index e9b8e6df8e..6ab4840c48 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+
 cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
index 69238a9f77..c2538e8ede 100644
--- a/src/cpu/intel/microcode/microcode_blob.c
+++ b/src/cpu/intel/model_206ax/microcode_blob.c
@@ -18,5 +18,5 @@
  */
 
 unsigned microcode[] = {
-#include <microcode_blob.h>
+#include "microcode_blob.h"
 };