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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-06-07 00:17:25 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-12 05:31:04 +0200 |
| commit | 0210119b4b95e84f954cfd6dc11aafbc187421af (patch) | |
| tree | 7ae26ebe87e407f294e6a947fb2bd19286bc5fbe /src/cpu | |
| parent | 26419285bf6643776d5ad6534db7d0422758efb2 (diff) | |
| download | coreboot-0210119b4b95e84f954cfd6dc11aafbc187421af.tar.xz | |
Add support for Intel Ibex Peak (Mobile 5) southbridge
Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3397
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/x86/smm/smmrelocate.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 16d4b9fde0..b42ac5da60 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -37,6 +37,8 @@ #include "../../../southbridge/intel/sch/sch.h" #elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 #include "../../../southbridge/intel/bd82x6x/pch.h" +#elif CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK +#include "../../../southbridge/intel/ibexpeak/pch.h" #elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX #include "../../../southbridge/intel/i82801ix/i82801ix.h" #else @@ -48,6 +50,9 @@ #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM +#include <northbridge/intel/nehalem/nehalem.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #else #error "Northbridge must define TSEG_BAR." #endif |