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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-23 18:48:27 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-23 18:48:27 +0000 |
| commit | 16db6c3486fba7292bade3233df96b4ab2ecc889 (patch) | |
| tree | e862728c6b0e9e6eb7e11fd8d1d813981d23df6b /src/cpu | |
| parent | d6b4f1cd0ad43d29fe925a6cc6951f205a8ead50 (diff) | |
| download | coreboot-16db6c3486fba7292bade3233df96b4ab2ecc889.tar.xz | |
Whitespace/typo/cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/model_gx2/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/amd/model_lx/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/x86/32bit/entry32.inc | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/amd/model_gx2/cache_as_ram.inc b/src/cpu/amd/model_gx2/cache_as_ram.inc index 09a7541676..433576c737 100644 --- a/src/cpu/amd/model_gx2/cache_as_ram.inc +++ b/src/cpu/amd/model_gx2/cache_as_ram.inc @@ -184,7 +184,7 @@ done_cache_as_ram_main: /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) /* post 11 */ + post_code(0x11) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -201,7 +201,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) /* post fail ee */ + post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc index b592bc51b9..a2e8f87e64 100644 --- a/src/cpu/amd/model_lx/cache_as_ram.inc +++ b/src/cpu/amd/model_lx/cache_as_ram.inc @@ -210,7 +210,7 @@ done_cache_as_ram_main: /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) /* post 11 */ + post_code(0x11) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -227,7 +227,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) /* post fail ee */ + post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index abb4a97236..de3b6cdfaa 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -51,7 +51,7 @@ __protected_start: /* Save the BIST value */ movl %eax, %ebp - post_code(0x10) /* post 10 */ + post_code(0x10) movw $ROM_DATA_SEG, %ax movw %ax, %ds |