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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-04 10:42:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:19:18 +0000 |
| commit | 2ea1c9b29e0549149905833e66bea875e932c5bf (patch) | |
| tree | 772703f42e0d1fe146cd8d312b75ead1ab662639 /src/cpu | |
| parent | 09ccd418f40bad87098e71411e408bf9b5c69881 (diff) | |
| download | coreboot-2ea1c9b29e0549149905833e66bea875e932c5bf.tar.xz | |
cpu/intel/haswell: Link monotonic_timer.c in early stages
This is needed for SPI flash console in bootblock/romstage/postcar.
Change-Id: I18253cc028e87cd31879d722a6d788917e9c97b3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 1e7d226c51..fa467e5a8b 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -17,6 +17,9 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y) +bootblock-y += monotonic_timer.c +romstage-y += monotonic_timer.c +postcar-y += monotonic_timer.c ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c endif |