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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-02-28 00:24:15 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-03-31 11:54:37 +0200 |
| commit | 325b92f64a62f355715a45470e41407ce3c39c1e (patch) | |
| tree | a86107ccafc56b5a879d554cea975965bba3f7e2 /src/cpu | |
| parent | 5a660ca2293cbf4c1ae44a2f37f9f389124eb749 (diff) | |
| download | coreboot-325b92f64a62f355715a45470e41407ce3c39c1e.tar.xz | |
Intel cpus: cache actual size of the Flash ROM device
Cache was enabled for the last 4 MB below 4 GB when ramstage is
loaded. This does not cover the case of a 8 MB Flash and could
overlap with some system device placed at high memory.
Use the actual device size for the cache region. Mainboard
may override this with Kconfig CACHE_ROM_SIZE if necessary.
Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/641
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 08f5b1138d..ed207db7b1 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -25,6 +25,9 @@ #define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +/* Base address to cache all of Flash ROM, just below 4GB. */ +#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -203,13 +206,13 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable caching and Speculative Reads for the last 4MB. */ + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr |