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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-09 09:37:49 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-15 05:31:29 +0000 |
| commit | 5bc641afebda5fd274ba713add4145651d9bc71d (patch) | |
| tree | 849f5712a83c5eb895ae3aee24a26509c8a8421b /src/cpu | |
| parent | b3267e002e798e90ca09b11e42ea8949dccde2e7 (diff) | |
| download | coreboot-5bc641afebda5fd274ba713add4145651d9bc71d.tar.xz | |
cpu/intel: Refactor platform_enter_postcar()
There are benefits in placing the postcar_frame structure
in .bss and returning control to romstage_main().
Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/car/romstage.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 89052d6be6..f6b62192f1 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -22,6 +22,21 @@ #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 +static struct postcar_frame early_mtrrs; + +/* prepare_and_run_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +static void prepare_and_run_postcar(struct postcar_frame *pcf) +{ + if (postcar_frame_init(pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + fill_postcar_frame(pcf); + + run_postcar_phase(pcf); + /* We do not return here. */ +} + static void romstage_main(unsigned long bist) { int i; @@ -52,7 +67,8 @@ static void romstage_main(unsigned long bist) printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - platform_enter_postcar(); + prepare_and_run_postcar(&early_mtrrs); + /* We do not return here. */ } #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) |