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| author | Li-Ta Lo <ollie@lanl.gov> | 2004-05-24 19:04:47 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2004-05-24 19:04:47 +0000 |
| commit | 9da7ff91f5e2cd428451ebd7477025e1dad7b716 (patch) | |
| tree | 7fa65ea59a7c246bf7cb00211a6c4b4425f6809e /src/cpu | |
| parent | 7b095aa1d932099f11800efaf1a5f431e8c8acef (diff) | |
| download | coreboot-9da7ff91f5e2cd428451ebd7477025e1dad7b716.tar.xz | |
added AGP support for AMD K8
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/k8/earlymtrr.c | 6 | ||||
| -rw-r--r-- | src/cpu/k8/earlymtrr.inc | 2 | ||||
| -rw-r--r-- | src/cpu/p6/mtrr.c | 33 |
3 files changed, 32 insertions, 9 deletions
diff --git a/src/cpu/k8/earlymtrr.c b/src/cpu/k8/earlymtrr.c index 2138e3fefe..16cd809f97 100644 --- a/src/cpu/k8/earlymtrr.c +++ b/src/cpu/k8/earlymtrr.c @@ -30,7 +30,7 @@ static void early_mtrr_init(void) /* Enable the access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(msr); + wrmsr(SYSCFG_MSR, msr); /* Inialize all of the relevant msrs to 0 */ msr.lo = 0; @@ -43,7 +43,7 @@ static void early_mtrr_init(void) /* Disable the access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(msr); + wrmsr(SYSCFG_MSR, msr); /* Enable memory access for 0 - 1MB using top_mem */ msr.hi = 0; @@ -87,7 +87,7 @@ static void early_mtrr_init(void) /* Enale the MTRRs in SYSCFG */ msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrrVarDramEn; + msr.lo |= SYSCFG_MSR_MtrrVarDramEn; wrmsr(SYSCFG_MSR, msr); /* Enable the cache */ diff --git a/src/cpu/k8/earlymtrr.inc b/src/cpu/k8/earlymtrr.inc index d5c754742b..81376bfb01 100644 --- a/src/cpu/k8/earlymtrr.inc +++ b/src/cpu/k8/earlymtrr.inc @@ -89,7 +89,7 @@ enable_mtrr: /* Enable the MTRRs and IORRs in SYSCFG */ movl $SYSCFG_MSR, %ecx rdmsr - /* Don't enable SYSCFG_MSR_MtrrFixDramEn) untill we have done with VGA BIOS */ + /* Don't enable SYSCFG_MSR_MtrrFixDramEn untill we have done with VGA BIOS */ orl $(SYSCFG_MSR_MtrrVarDramEn), %eax wrmsr diff --git a/src/cpu/p6/mtrr.c b/src/cpu/p6/mtrr.c index 89465c6209..36286608e8 100644 --- a/src/cpu/p6/mtrr.c +++ b/src/cpu/p6/mtrr.c @@ -300,6 +300,14 @@ void setup_mtrrs(struct mem_range *mem) struct mem_range *memp; unsigned long range_startk, range_sizek; unsigned int reg; + msr_t msr; + +#if defined(k7) || defined(k8) + /* Enable the access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); +#endif printk_debug("\n"); /* Initialized the fixed_mtrrs to uncached */ @@ -318,16 +326,31 @@ void setup_mtrrs(struct mem_range *mem) break; } -#if defined(k7) || defined(k8) -#warning "FIXME: dealing with RdMEM/WrMEM for Athlon/Opteron" -#endif - printk_debug("Setting fixed MTRRs(%d-%d) type: WB\n", start_mtrr, last_mtrr); - set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK); + + +#if defined(k7) || defined(k8) + set_fixed_mtrrs(start_mtrr, last_mtrr, + MTRR_TYPE_WRBACK | MTRR_READ_MEM| MTRR_WRITE_MEM); +#else + set_fixed_mtrrs(start_mtrr, last_mtrr, + MTRR_TYPE_WRBACK); +#endif } printk_debug("DONE fixed MTRRs\n"); +#if defined(k7) || defined(k8) + /* Disable the access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + /* Enale the RdMEM and WrMEM bits in SYSCFG */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); +#endif + /* Cache as many memory areas as possible */ /* FIXME is there an algorithm for computing the optimal set of mtrrs? * In some cases it is definitely possible to do better. |