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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-17 20:51:08 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-26 21:08:41 +0000
commitcd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch)
treeb0438431df0943ab5f0fa9d80a99fc265130ac23 /src/cpu
parent16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff)
downloadcoreboot-cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf.tar.xz
soc/intel: Use common romstage code
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/car/romstage.c16
1 files changed, 0 insertions, 16 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index a0dc743806..ac81b021a8 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -15,7 +15,6 @@
#include <arch/romstage.h>
#include <bootblock_common.h>
#include <console/console.h>
-#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <arch/symbols.h>
@@ -29,21 +28,6 @@
static struct postcar_frame early_mtrrs;
-/* prepare_and_run_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-static void prepare_and_run_postcar(struct postcar_frame *pcf)
-{
- if (postcar_frame_init(pcf, 0))
- die("Unable to initialize postcar frame.\n");
-
- fill_postcar_frame(pcf);
-
- postcar_frame_common_mtrrs(pcf);
-
- run_postcar_phase(pcf);
- /* We do not return here. */
-}
-
static void romstage_main(unsigned long bist)
{
int i;