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authorDavid Hendricks <dhendrix@chromium.org>2012-12-27 13:50:32 -0800
committerRonald G. Minnich <rminnich@gmail.com>2012-12-29 15:33:17 +0100
commitf1dfb2eb94f86a2168776d9ea5b098d25e5b369c (patch)
tree16d5646e1b5728da7f412e20199b036199e1d132 /src/cpu
parent37a85163700f7183c786bab1004ff47cc90e9d9e (diff)
downloadcoreboot-f1dfb2eb94f86a2168776d9ea5b098d25e5b369c.tar.xz
move iRAM config variable to exynos5250 Kconfig
Since these don't seem very generic and depend on the BL1, let's move them to the CPU-specific Kconfig. Change-Id: I33059b7db30d35a1853918a580f312e50a3499fa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2077 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/samsung/Kconfig26
-rw-r--r--src/cpu/samsung/exynos5250/Kconfig20
2 files changed, 20 insertions, 26 deletions
diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig
index 3a14ab86e8..4a09ca3cdb 100644
--- a/src/cpu/samsung/Kconfig
+++ b/src/cpu/samsung/Kconfig
@@ -15,32 +15,6 @@ config SKIP_LOWLEVEL_INIT
Certain functions (ie PLL init) and processor features may already be
handled by masked ROM code.
-config IRAM_BOTTOM
- hex
- default 0x02020000
-
-# FIXME(dhendrix): 0x02050000 was in the u-boot sources, but the docs say the
-# iRAM range is 0x0202_0000 - 0x0207_7fff (352KB).
-#config IRAM_TOP
-# hex
-# default 0x02050000
-config IRAM_TOP
- hex
- default 0x02077fff
-
-config SYS_INIT_SP_ADDR
- hex
- default 0x0204F800
-
-config IRAM_STACK
- hex
- default SYS_INIT_SP_ADDR
-
-# FIXME(dhendrix): what should this really be?
-config XIP_ROM_SIZE
- hex
- default 0x20000
-
if CPU_SAMSUNG_EXYNOS5
source src/cpu/samsung/exynos5250/Kconfig
endif
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index 8d4ba2dd0a..c2d9b9fddc 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -26,3 +26,23 @@ config RAMBASE
config RAMTOP
hex
default 0x40100000
+
+config IRAM_BOTTOM
+ hex
+ default 0x02020000
+
+config IRAM_TOP
+ hex
+ default 0x02077fff
+
+config SYS_INIT_SP_ADDR
+ hex
+ default 0x0204F800
+
+config IRAM_STACK
+ hex
+ default SYS_INIT_SP_ADDR
+
+config XIP_ROM_SIZE
+ hex "ROM stage (BL2) size"
+ default 0x20000