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| author | Bora Guvendik <bora.guvendik@intel.com> | 2020-03-10 17:50:28 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-20 09:39:27 +0000 |
| commit | 12b835050f0af9341b257560b60a8060c8fad328 (patch) | |
| tree | b0b9ccdfc955c7f178f2dc2cf88462a19e15a856 /src/cpu | |
| parent | 70ea3b9141ee92177c1a1185a7e6a468fd59bc85 (diff) | |
| download | coreboot-12b835050f0af9341b257560b60a8060c8fad328.tar.xz | |
soc/intel: Enable GPIO functions in verstage
Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.
BUG=b:151102807
TEST=make build successful
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions