eric patch

        1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

14 files changed, 1245 insertions, 92 deletions

diff --git a/src/cpu/amd/car/cache_as_ram_post.c b/src/cpu/amd/car/cache_as_ram_post.c
index 66ca9fdf96..6a129b258a 100644
--- a/src/cpu/amd/car/cache_as_ram_post.c
+++ b/src/cpu/amd/car/cache_as_ram_post.c
@@ -1,4 +1,5 @@
 /* by yhlu 6.2005 */
+/* be warned, this file will be used other cores and core0/node0 */
         __asm__ volatile (
 	/* 
 	FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index b75025b4c8..3c526e78ca 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -192,6 +192,7 @@ static void init_ecc_memory(unsigned node_id)
 	/* If ecc support is not enabled don't touch memory */
 	dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
 	if (!(dcl & DCL_DimmEccEn)) {
+		printk_debug("ECC Disabled\n");
 		return;
 	}
 
@@ -226,7 +227,9 @@ static void init_ecc_memory(unsigned node_id)
 	disable_lapic();
 
 	/* Walk through 2M chunks and zero them */
-	for(basek = begink; basek < endk; basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
+	for(basek = begink; basek < endk; 
+		basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) 
+	{
 		unsigned long limitk;
 		unsigned long size;
 		void *addr;
@@ -255,12 +258,13 @@ static void init_ecc_memory(unsigned node_id)
 		}
 		size = (limitk - basek) << 10;
 		addr = map_2M_page(basek >> 11);
-		addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
 		if (addr == MAPPING_ERROR) {
+			printk_err("Cannot map page: %x\n", basek >> 11);
 			continue;
 		}
 
 		/* clear memory 2M (limitk - basek) */
+		addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
 		clear_memory(addr, size);
 	}
 	/* Restore the normal state */
@@ -319,19 +323,16 @@ static inline void k8_errata(void)
 		}	
 		wrmsr(NB_CFG_MSR, msr);
 	}
-// AMD_D0_SUPPORT	
+	
+	/* Erratum 97 ... */
 	if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
-		/* D0 later don't need it */
-		/* Erratum 97 ... */
 		msr = rdmsr_amd(DC_CFG_MSR);
 		msr.lo |= 1 << 3;
 		wrmsr_amd(DC_CFG_MSR, msr);
-	}
-		
-//AMD_D0_SUPPORT
-	if(is_cpu_pre_d0()) {
-		/*D0 later don't need it */
-		/* Erratum 94 ... */
+	}	
+	
+	/* Erratum 94 ... */
+	if (is_cpu_pre_d0()) {
 		msr = rdmsr_amd(IC_CFG_MSR);
 		msr.lo |= 1 << 11;
 		wrmsr_amd(IC_CFG_MSR, msr);
@@ -339,37 +340,51 @@ static inline void k8_errata(void)
 
 	/* Erratum 91 prefetch miss is handled in the kernel */
 
-//AMD_D0_SUPPORT
+	/* Erratum 106 ... */
+	msr = rdmsr_amd(LS_CFG_MSR);
+	msr.lo |= 1 << 25;
+	wrmsr_amd(LS_CFG_MSR, msr);
+
+	/* Erratum 107 ... */
+	msr = rdmsr_amd(BU_CFG_MSR);
+	msr.hi |= 1 << (43 - 32);
+	wrmsr_amd(BU_CFG_MSR, msr);
+
 	if(is_cpu_d0()) {
 		/* Erratum 110 ...*/
 		msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
 		msr.hi |=1;
 		wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
-	}
+ 	}
 
-//AMD_E0_SUPPORT
-	if(!is_cpu_pre_e0()) {
-                /* Erratum 110 ...*/
+	if (!is_cpu_pre_e0()) {
+		/* Erratum 110 ... */
                 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
                 msr.hi |=1;
                 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	}
+
+	/* Erratum 122 */
+	msr = rdmsr(HWCR_MSR);
+	msr.lo |= 1 << 6;
+	wrmsr(HWCR_MSR, msr);
+	
 }
 
 void model_fxx_init(device_t dev)
 {
 	unsigned long i;
 	msr_t msr;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	struct node_core_id id;
-        unsigned siblings;
+	unsigned siblings;
 	id.coreid=0;
 #else
 	unsigned nodeid;
 #endif
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache(); 
+	x86_enable_cache();
 	amd_setup_mtrrs();
 	x86_mtrr_check();
 
@@ -386,11 +401,12 @@ void model_fxx_init(device_t dev)
 	
 	enable_cache();
 
-#if CONFIG_LOGICAL_CPUS==1
-//AMD_DUAL_CORE_SUPPORT
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+#if CONFIG_LOGICAL_CPUS == 1
         siblings = cpuid_ecx(0x80000008) & 0xff;
 
-//	id = get_node_core_id((!is_cpu_pre_e0())? read_nb_cfg_54():0);
 	id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
 
        	if(siblings>0) {
@@ -407,24 +423,24 @@ void model_fxx_init(device_t dev)
                	wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	} 
         
+
 	/* Is this a bad location?  In particular can another node prefecth
 	 * data from this node before we have initialized it?
 	 */
-	if(id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core0
+	if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
 #else
-	/* For now there is a 1-1 mapping between node_id and cpu_id */
-	nodeid = lapicid() & 0x7;
+	/* Is this a bad location?  In particular can another node prefecth
+	 * data from this node before we have initialized it?
+	 */
+	nodeid = lapicid() & 0xf;
 	init_ecc_memory(nodeid);
 #endif
-	
-	/* Enable the local cpu apics */
-	setup_lapic();
 
 #if CONFIG_LOGICAL_CPUS==1
-//AMD_DUAL_CORE_SUPPORT
         /* Start up my cpu siblings */
 //	if(id.coreid==0)  amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
 #endif
+
 }
 
 static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/amd/model_fxx/model_fxx_msr.h b/src/cpu/amd/model_fxx/model_fxx_msr.h
index c8d57bee1a..b4795cbbb2 100644
--- a/src/cpu/amd/model_fxx/model_fxx_msr.h
+++ b/src/cpu/amd/model_fxx/model_fxx_msr.h
@@ -3,6 +3,7 @@
 
 #define HWCR_MSR			0xC0010015
 #define NB_CFG_MSR			0xC001001f
+#define LS_CFG_MSR                      0xC0011020
 #define IC_CFG_MSR			0xC0011021
 #define DC_CFG_MSR			0xC0011022
 #define BU_CFG_MSR			0xC0011023
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index de4ed988c2..e57bb3bec7 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -96,26 +96,32 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
 		return;
 	}
 	printk_debug("Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
-		     start_mtrr, last_mtrr);
+		start_mtrr, last_mtrr);
 	set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
 	
 }
 
+extern void enable_fixed_mtrr(void);
+
 void amd_setup_mtrrs(void)
 {
+	unsigned long address_bits;
 	struct mem_state state;
 	unsigned long i;
 	msr_t msr;
 
+
 	/* Enable the access to AMD RdDram and WrDram extension bits */
+	disable_cache();
 	msr = rdmsr(SYSCFG_MSR);
 	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
 	wrmsr(SYSCFG_MSR, msr);
+	enable_cache();
 
 	printk_debug("\n");
 	/* Initialized the fixed_mtrrs to uncached */
 	printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n", 
-		     0, NUM_FIXED_RANGES);
+		0, NUM_FIXED_RANGES);
 	set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
 
 	/* Except for the PCI MMIO hole just before 4GB there are no
@@ -127,6 +133,7 @@ void amd_setup_mtrrs(void)
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_fixed_mtrr_resource, &state);
 	printk_debug("DONE fixed MTRRs\n");
+
 	if (state.mmio_basek > state.tomk) {
 		state.mmio_basek = state.tomk;
 	}
@@ -164,10 +171,17 @@ void amd_setup_mtrrs(void)
 	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
 	wrmsr(SYSCFG_MSR, msr);
 
+	enable_fixed_mtrr();
+
 	enable_cache();
 
+	/* FIXME we should probably query the cpu for this
+	 * but so far this is all any recent AMD cpu has supported.
+	 */
+	address_bits = 40;
+
 	/* Now that I have mapped what is memory and what is not
 	 * Setup the mtrrs so we can cache the memory.
 	 */
-	x86_setup_mtrrs();
+	x86_setup_var_mtrrs(address_bits);
 }
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index 55504a1049..474d025799 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -30,7 +30,7 @@ static void model_f0x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs();
+	x86_setup_mtrrs(36);
 	x86_mtrr_check();
 	
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 53cee4fe68..42dff1e276 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -30,7 +30,7 @@ static void model_f1x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs();
+	x86_setup_mtrrs(36);
 	x86_mtrr_check();
 	
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index 4f69d81d2a..f019ea4473 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -34,7 +34,7 @@ static void model_f2x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs();
+	x86_setup_mtrrs(36);
 	x86_mtrr_check();
 	
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index a89e7d1782..20b8518c7c 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs();
+	x86_setup_mtrrs(36);
 	x86_mtrr_check();
 	
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f4x/Config.lb b/src/cpu/intel/model_f4x/Config.lb
new file mode 100644
index 0000000000..66f6ceb00f
--- /dev/null
+++ b/src/cpu/intel/model_f4x/Config.lb
@@ -0,0 +1,12 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+driver model_f4x_init.o
diff --git a/src/cpu/intel/model_f4x/microcode_MBDF410D.h b/src/cpu/intel/model_f4x/microcode_MBDF410D.h
new file mode 100644
index 0000000000..9266ce5c34
--- /dev/null
+++ b/src/cpu/intel/model_f4x/microcode_MBDF410D.h
@@ -0,0 +1,1024 @@
+0x00000001, /* Header Version	*/

+0x0000000d, /* Patch ID		*/

+0x11032004, /* DATE		*/

+0x00000f41, /* CPUID		*/

+0xa3430d74, /* Checksum		*/

+0x00000001, /* Loader Version	*/

+0x000000bd, /* Platform ID	*/

+0x00000fd0, /* Data size	*/

+0x00001000, /* Total size	*/

+0x00000000, /* reserved		*/

+0x00000000, /* reserved		*/

+0x00000000, /* reserved		*/

+0x23869663,

+0x00e8d132,

+0xc1efa329,

+0x20662968,

+0xb833cad6,

+0x78012780,

+0x0971cf44,

+0xda1410ae,

+0xece61219,

+0x5ec0a10c,

+0x5a1c529c,

+0x9b5e4fac,

+0x35fee068,

+0x24bb3539,

+0xa6c23421,

+0x0309a01d,

+0x80331c7b,

+0x960d5da2,

+0x56d31115,

+0xdaadb98b,

+0x8d5c0ca8,

+0xc1fc4f86,

+0xef6ee956,

+0x512c9483,

+0x08a9c125,

+0x03b95162,

+0x6499668c,

+0x25e15127,

+0xfb4f0f0b,

+0x10d1b2c3,

+0x542be728,

+0xa0f11cc9,

+0xa5bc6bd2,

+0xf3b7cc86,

+0xe4a91466,

+0x41eceee1,

+0x5beb249b,

+0x6ab82791,

+0x2c5a86ac,

+0x90c2865d,

+0x4702c4a5,

+0xbddad5f1,

+0xb2e224fb,

+0x0ffb50d3,

+0x13c6933c,

+0xc573b9df,

+0x908510f6,

+0xca6f3a9e,

+0x2049f489,

+0xe20b8848,

+0xfd659d6e,

+0xc9afd397,

+0x1432aa70,

+0x62c3e20c,

+0xee6dda59,

+0xe8601135,

+0xa9e30f8e,

+0x691b59e5,

+0x0446816b,

+0xd63a3f0c,

+0x5d1b9d99,

+0xfe8d9637,

+0xee61a0a4,

+0xeeae5aa0,

+0x709d78e6,

+0x5468e7fb,

+0x7e0f2dc3,

+0x632591e1,

+0x990864bb,

+0x413a220b,

+0x5285bdcd,

+0xb7323fa6,

+0xfe0098ce,

+0xd05d24b2,

+0x51ee2e1e,

+0x0078c207,

+0x9d1e1514,

+0x1be23c59,

+0xa80398e4,

+0xe0fa94c8,

+0x2b2f841e,

+0x21144f67,

+0x0a6a1413,

+0xfa30499a,

+0xba49558e,

+0x1607d767,

+0xebd70987,

+0x00cb016d,

+0xac1de18a,

+0xfcde8566,

+0x23f51d05,

+0xb7368509,

+0x9b1947fd,

+0x0d0d3c22,

+0xfbeab67d,

+0xfc963120,

+0x0aeae56b,

+0x0dbe2aeb,

+0x6d4ba825,

+0xab4b8dae,

+0x23bbe7a0,

+0x53d38f2e,

+0x6ee7bed3,

+0x39869966,

+0x8e36076d,

+0x410dca57,

+0x133c4861,

+0xcc2920d0,

+0xb1cfc172,

+0xd3c2e94b,

+0x8cdb7550,

+0xcb14be86,

+0x1c72bb42,

+0x469a6066,

+0x912f65eb,

+0x173ac7b9,

+0xfa02afca,

+0x23fc44f2,

+0xbbf0c89f,

+0xa018ba5f,

+0x950654d1,

+0x1b6d7652,

+0xb2a04767,

+0x86630316,

+0xff3fd7b3,

+0x9c9b3aba,

+0xb7d6115b,

+0x7c7a354c,

+0x1761b195,

+0xc54b49dd,

+0x2e0f5f20,

+0xaf1e90b2,

+0x07056032,

+0x46ccdd94,

+0xcc751ec5,

+0x4774af8a,

+0x24a3dba1,

+0xa388bccc,

+0xacd1c25a,

+0x4ee406c1,

+0x9861931a,

+0x5bae36e2,

+0xafc6e087,

+0x8d36cd1b,

+0x25f894d1,

+0xd749fdaa,

+0x3cef917d,

+0xb85440c2,

+0x4d22a2bf,

+0x19703ee4,

+0xa5fd9e1e,

+0x76062779,

+0x14031f62,

+0x6e309271,

+0x55476f65,

+0xb4fd2411,

+0x554882db,

+0xee9d4d38,

+0x57faf730,

+0x730e0285,

+0xb882d382,

+0xc156852d,

+0xf2db8f7a,

+0xea52f3e4,

+0x323430d1,

+0x51ea5fe9,

+0x0929d601,

+0x8e6740cf,

+0x69c456e1,

+0xd9e2f5c1,

+0x0124bf3b,

+0x0220f415,

+0xfbe91365,

+0x2bc82d06,

+0x0a31f25c,

+0xbeaf32af,

+0x3c2175b7,

+0xe8f67a0e,

+0x177bb8fa,

+0x33b86eb3,

+0x3ba0e579,

+0x368fc48b,

+0xe6665da8,

+0x688bfd43,

+0x48448000,

+0xc5c99d34,

+0xab99cfeb,

+0x1ce9c58d,

+0x773ae448,

+0x3534d849,

+0x6d86470f,

+0x306db8d0,

+0x550c15ff,

+0x7a2c439a,

+0xe6f1b78f,

+0x0bf4cdd7,

+0xfbcab3d7,

+0x402e87ec,

+0xf4ee5874,

+0xc03c70d9,

+0x3b9ed9e6,

+0x04ef67e0,

+0xd04ae924,

+0xf6845607,

+0x5e58c954,

+0xc2fdf283,

+0xc558ae4e,

+0x8300ece1,

+0x7bbaea80,

+0xc5d0b0f1,

+0xfc9e8004,

+0xfcea494a,

+0x04f4eb47,

+0x129f505d,

+0xccbae019,

+0x59c0616f,

+0xaaba53a8,

+0x19d8a002,

+0x361fb171,

+0x00c4aee2,

+0x6bb0dfb0,

+0xc03d6b9a,

+0xabaed6fb,

+0xa23c48fe,

+0x50866e98,

+0xbb499854,

+0xb5730aad,

+0xbe89d93c,

+0xe6d35886,

+0x7ae05c20,

+0xc2708cbd,

+0xf8f18059,

+0xf492c48e,

+0x14121e3d,

+0x9e9dc5a7,

+0xafa3ef3a,

+0x17535114,

+0x08296547,

+0xe1ab5d3c,

+0x2e51d954,

+0x0e6953db,

+0xde0ea136,

+0xd1f37944,

+0x3074f7ed,

+0x3b196093,

+0x0efb3b56,

+0x3b904c2c,

+0xcef179ee,

+0xc854e7f5,

+0x48aa28ce,

+0x1c0cb17e,

+0xae4236b2,

+0x87c5dc18,

+0x7832ec05,

+0xc4212949,

+0xca5a40d2,

+0x8e8f431d,

+0x328df52b,

+0xe4dd2524,

+0x7b8ae78a,

+0x17ba24a3,

+0x25eb59d5,

+0x1a341b63,

+0x45f1e3f2,

+0x0e2d9cf8,

+0xa66c17e8,

+0x515bc934,

+0xfea866d3,

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diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
new file mode 100644
index 0000000000..649638670d
--- /dev/null
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -0,0 +1,58 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+static uint32_t microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+	
+#include "microcode_MBDF410D.h"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+
+static void model_f4x_init(device_t cpu)
+{
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+	x86_setup_mtrrs(36);
+	x86_mtrr_check();
+	
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+	/* Start up my cpu siblings */
+	intel_sibling_init(cpu);
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init = model_f4x_init,
+};
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0f41 }, /* Xeon */
+	{ 0, 0 },
+};
+
+static struct cpu_driver model_f4x __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
diff --git a/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb b/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
index 0b794338a2..2637c86594 100644
--- a/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
+++ b/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
@@ -1,3 +1,4 @@
 config chip.h
 object socket_mPGA604_800Mhz.o
 dir /cpu/intel/model_f3x
+dir /cpu/intel/model_f4x
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index c435b2edd5..105f7c49df 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -37,8 +37,8 @@ static void disable_var_mtrr(unsigned reg)
 	wrmsr(MTRRphysMask_MSR(reg), zero);
 }
 
-static void set_var_mtrr(unsigned reg, unsigned base, unsigned size,
-			 unsigned type)
+static void set_var_mtrr(
+	unsigned reg, unsigned base, unsigned size, unsigned type)
 
 {
 	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
@@ -76,7 +76,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
 	msr.lo = 0;
 	msr.hi = 0;
 	unsigned long msr_nr;
-	for (msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
+	for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
 		wrmsr(msr_nr, msr);
 	}
 
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 59f9ca1e91..1226713cf5 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -22,9 +22,14 @@
  *
  * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
  */
+
 /*
-	2005.1 yhlu add NC support to spare mtrrs for 64G memory stored
+        2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed
+	2005.6 Eric add address bit in x86_setup_mtrrs
+	2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs,
+		for AMD, it will not use x86_setup_fixed_mtrrs
 */
+
 #include <stddef.h>
 #include <console/console.h>
 #include <device/device.h>
@@ -32,19 +37,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 
-#warning "FIXME I do not properly handle address more than 36 physical address bits"
-
-//#define k8 0
-#define k8 1
-
-#if k8
-# define ADDRESS_BITS 40
-#else
-# define ADDRESS_BITS 36
-#endif
-#define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32)
-#define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1)
-
 static unsigned int mtrr_msr[] = {
 	MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
 	MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
@@ -52,7 +44,7 @@ static unsigned int mtrr_msr[] = {
 };
 
 
-static void enable_fixed_mtrr(void)
+void enable_fixed_mtrr(void)
 {
 	msr_t msr;
 
@@ -71,21 +63,26 @@ static void enable_var_mtrr(void)
 }
 
 /* setting variable mtrr, comes from linux kernel source */
-static void set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
+static void set_var_mtrr(
+	unsigned int reg, unsigned long basek, unsigned long sizek, 
+	unsigned char type, unsigned address_bits)
 {
 	msr_t base, mask;
+	unsigned address_mask_high;
+
+	address_mask_high = ((1u << (address_bits - 32u)) - 1u);
 
 	base.hi = basek >> 22;
 	base.lo  = basek << 10;
 
-       //printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
+	printk_spew("ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
 
 	if (sizek < 4*1024*1024) {
-		mask.hi = ADDRESS_MASK_HIGH;
+		mask.hi = address_mask_high;
 		mask.lo = ~((sizek << 10) -1);
 	}
 	else {
-		mask.hi = ADDRESS_MASK_HIGH & (~((sizek >> 22) -1));
+		mask.hi = address_mask_high & (~((sizek >> 22) -1));
 		mask.lo = 0;
 	}
 
@@ -219,7 +216,7 @@ static unsigned fixed_mtrr_index(unsigned long addrk)
 
 static unsigned int range_to_mtrr(unsigned int reg, 
 	unsigned long range_startk, unsigned long range_sizek,
-	unsigned long next_range_startk, unsigned char type)
+	unsigned long next_range_startk, unsigned char type, unsigned address_bits)
 {
 	if (!range_sizek || (reg >= BIOS_MTRRS)) {
 		return reg;
@@ -235,11 +232,11 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		}
 		sizek = 1 << align;
 		printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n",
-			reg, range_startk >>10, sizek >> 10, 
-			(type==MTRR_TYPE_UNCACHEABLE) ? "NC" :
-			    ((type==MTRR_TYPE_WRBACK) ? "WB" : "Other")
+			reg, range_startk >>10, sizek >> 10,
+			(type==MTRR_TYPE_UNCACHEABLE)?"UC":
+			    ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
 			);
-		set_var_mtrr(reg++, range_startk, sizek, type);
+		set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
 		range_startk += sizek;
 		range_sizek -= sizek;
 		if (reg >= BIOS_MTRRS)
@@ -279,6 +276,7 @@ struct var_mtrr_state {
 	unsigned long range_startk, range_sizek;
 	unsigned int reg;
 	unsigned long hole_startk, hole_sizek;
+	unsigned address_bits;
 };
 
 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
@@ -300,47 +298,68 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
 	}
 	/* Write the range mtrrs */
 	if (state->range_sizek != 0) {
-		if(state->hole_sizek == 0) {
-			// we need to put that on to hole.
-	                unsigned long endk = basek + sizek;
+		if (state->hole_sizek == 0) {
+			/* We need to put that on to hole */
+			unsigned long endk = basek + sizek;
 			state->hole_startk = state->range_startk + state->range_sizek;
-			state->hole_sizek = basek - state->hole_startk;
-	                state->range_sizek = endk - state->range_startk;
+			state->hole_sizek  = basek - state->hole_startk;
+			state->range_sizek = endk - state->range_startk;
 			return;
 		}
-		state->reg = range_to_mtrr(state->reg, state->range_startk, state->range_sizek, basek, MTRR_TYPE_WRBACK);
-		state->reg = range_to_mtrr(state->reg, state->hole_startk, state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE);
+		state->reg = range_to_mtrr(state->reg, state->range_startk, 
+			state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
+		state->reg = range_to_mtrr(state->reg, state->hole_startk, 
+			state->hole_sizek, basek,  MTRR_TYPE_UNCACHEABLE, state->address_bits);
 		state->range_startk = 0;
 		state->range_sizek = 0;
                 state->hole_startk = 0;
                 state->hole_sizek = 0;
 	}
-	/* Allocate an msr */
+	/* Allocate an msr */  
+	printk_spew(" Allocate an msr - basek = %d, sizek = %d,\n", basek, sizek);
 	state->range_startk = basek;
 	state->range_sizek  = sizek;
 }
 
-void x86_setup_mtrrs(void)
+void x86_setup_fixed_mtrrs(void)
+{
+        /* Try this the simple way of incrementally adding together
+         * mtrrs.  If this doesn't work out we can get smart again 
+         * and clear out the mtrrs.
+         */
+        struct var_mtrr_state var_state;
+
+        printk_debug("\n");
+        /* Initialized the fixed_mtrrs to uncached */
+        printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
+	        0, NUM_FIXED_RANGES);
+        set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
+
+        /* Now see which of the fixed mtrrs cover ram.
+                 */
+        search_global_resources(
+		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
+		set_fixed_mtrr_resource, NULL);
+        printk_debug("DONE fixed MTRRs\n");
+
+        /* enable fixed MTRR */
+        printk_spew("call enable_fixed_mtrr()\n");
+        enable_fixed_mtrr();
+
+}
+void x86_setup_var_mtrrs(unsigned address_bits)
+/* this routine needs to know how many address bits a given processor
+ * supports.  CPUs get grumpy when you set too many bits in 
+ * their mtrr registers :(  I would generically call cpuid here
+ * and find out how many physically supported but some cpus are
+ * buggy, and report more bits then they actually support.
+ */
 {
 	/* Try this the simple way of incrementally adding together
 	 * mtrrs.  If this doesn't work out we can get smart again 
 	 * and clear out the mtrrs.
 	 */
 	struct var_mtrr_state var_state;
-#if !k8
-	printk_debug("\n");
-	/* Initialized the fixed_mtrrs to uncached */
-	printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n", 
-		0, NUM_FIXED_RANGES);
-	set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
-
-	/* Now see which of the fixed mtrrs cover ram.
-	 */
-	search_global_resources(
-		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
-		set_fixed_mtrr_resource, NULL);
-	printk_debug("DONE fixed MTRRs\n");
-#endif
 
 	/* Cache as many memory areas as possible */
 	/* FIXME is there an algorithm for computing the optimal set of mtrrs? 
@@ -351,28 +370,35 @@ void x86_setup_mtrrs(void)
 	var_state.hole_startk = 0;
 	var_state.hole_sizek = 0;
 	var_state.reg = 0;
+	var_state.address_bits = address_bits;
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_var_mtrr_resource, &var_state);
 
 	/* Write the last range */
-	var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, var_state.range_sizek, 0, MTRR_TYPE_WRBACK);
-	var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE);
+	var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, 
+		var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
+	var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
+		var_state.hole_sizek,  0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
 	printk_debug("DONE variable MTRRs\n");
 	printk_debug("Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
 	while(var_state.reg < MTRRS) {
-		set_var_mtrr(var_state.reg++, 0, 0, 0);
+		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
-	/* enable fixed MTRR */
-	printk_spew("call enable_fixed_mtrr()\n");
-	enable_fixed_mtrr();
 	printk_spew("call enable_var_mtrr()\n");
 	enable_var_mtrr();
 	printk_spew("Leave %s\n", __FUNCTION__);
 	post_code(0x6A);
 }
 
+void x86_setup_mtrrs(unsigned address_bits)
+{
+	x86_setup_fixed_mtrrs();
+	x86_setup_var_mtrrs(address_bits);
+}
+
+
 int x86_mtrr_check(void)
 {
 	/* Only Pentium Pro and later have MTRR */