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| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-04 12:06:05 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-09 19:35:12 +0000 |
| commit | 14714e1303a420f9e0bf0bb5bba2efaae2c52efb (patch) | |
| tree | c26b86718fb5de9ef1e2194071f640f51e0a1149 /src/cpu | |
| parent | b2a62622ba030162784c31865a4fcba0c03408c7 (diff) | |
| download | coreboot-14714e1303a420f9e0bf0bb5bba2efaae2c52efb.tar.xz | |
x86: link romstage like the other architectures
All the other architectures are using the memlayout
for linking romstage. Use that same method on x86
as well for consistency.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11510
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/x86/32bit/entry32.ld | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld deleted file mode 100644 index 471b5f7005..0000000000 --- a/src/cpu/x86/32bit/entry32.ld +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) |