cpu/intel: Make all Intel CPUs load microcode from CBFS

The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.

The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.

The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.

Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>

72 files changed, 390 insertions, 434 deletions

diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig
index 025ad3f81e..380869a610 100644
--- a/src/cpu/intel/ep80579/Kconfig
+++ b/src/cpu/intel/ep80579/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_EP80579
 	bool
 	select SSE
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index 080e2eec9c..b213c08c1e 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -7,3 +7,4 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c
index b1c1e22be0..22166b16ca 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -29,14 +29,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 
-static u32 microcode_updates[] = {
-	/*  Dummy terminator  */
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-};
-
 static void ep80579_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
@@ -45,7 +37,7 @@ static void ep80579_init(device_t dev)
 	x86_mtrr_check();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Enable the local cpu apics */
 	setup_lapic();
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
new file mode 100644
index 0000000000..cb95b1ae71
--- /dev/null
+++ b/src/cpu/intel/ep80579/microcode_blob.c
@@ -0,0 +1,13 @@
+/*
+ * We support updating microcode from CBFS, but do not have any microcode
+ * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
+ * CBFS, but this file can be later replaced without needing to recompile the
+ * coreboot.rom image.
+ */
+unsigned microcode_updates_ep80579[] = {
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index 22655c9532..1feb50495a 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -2,4 +2,4 @@
 ## One small file with the awesome super-power of updating the cpu microcode
 ## directly from CBFS. You have been WARNED!!!
 ################################################################################
-ramstage-y += microcode.c
\ No newline at end of file
+ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 83a412673f..c823eb81dd 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -29,16 +29,12 @@
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
 
-#ifdef __PRE_RAM__
-#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
-#include <arch/cbfs.h>
-#endif
-#else
-#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
+#if !defined(__PRE_RAM__)
 #include <cbfs.h>
-#endif
 #include <smp/spinlock.h>
 DECLARE_SPIN_LOCK(microcode_lock)
+#else
+#include <arch/cbfs.h>
 #endif
 
 struct microcode {
@@ -82,8 +78,6 @@ static inline u32 read_microcode_rev(void)
 	return msr.hi;
 }
 
-#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
-
 #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
 
 void intel_microcode_load_unlocked(const void *microcode_patch)
@@ -168,7 +162,7 @@ const void *intel_microcode_find(void)
 			update_size = m->total_size;
 		} else {
 			#if !defined(__ROMCC__)
-			printk(BIOS_WARNING, "Microcode has no valid size field!\n");
+			printk(BIOS_SPEW, "Microcode size field is 0\n");
 			#endif
 			update_size = 2048;
 		}
@@ -206,85 +200,3 @@ void intel_update_microcode_from_cbfs(void)
 	spin_unlock(&microcode_lock);
 #endif
 }
-
-#else /* !CONFIG_SUPPORT_CPU_UCODE_IN_CBFS */
-
-void intel_update_microcode(const void *microcode_updates)
-{
-	u32 eax;
-	u32 pf, rev, sig;
-	unsigned int x86_model, x86_family;
-	const struct microcode *m;
-	const char *c;
-	msr_t msr;
-
-	if (!microcode_updates) {
-#if !defined(__ROMCC__)
-		printk(BIOS_WARNING, "No microcode updates found.\n");
-#endif
-		return;
-	}
-
-	/* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
-	msr.lo = 0;
-	msr.hi = 0;
-	wrmsr(0x8B, msr);
-	eax = cpuid_eax(1);
-	msr = rdmsr(0x8B);
-	rev = msr.hi;
-	x86_model = (eax >>4) & 0x0f;
-	x86_family = (eax >>8) & 0x0f;
-	sig = eax;
-
-	pf = 0;
-	if ((x86_model >= 5)||(x86_family>6)) {
-		msr = rdmsr(0x17);
-		pf = 1 << ((msr.hi >> 18) & 7);
-	}
-#if !defined(__ROMCC__)
-	/* If this code is compiled with ROMCC we're probably in
-	 * the bootblock and don't have console output yet.
-	 */
-	printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n",
-			sig, pf, rev);
-#endif
-#if !defined(__ROMCC__) && !defined(__PRE_RAM__)
-	spin_lock(&microcode_lock);
-#endif
-
-	m = microcode_updates;
-	for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {
-		if ((m->sig == sig) && (m->pf & pf)) {
-			unsigned int new_rev;
-			msr.lo = (unsigned long)c + sizeof(struct microcode);
-			msr.hi = 0;
-			wrmsr(0x79, msr);
-
-			/* Read back the new microcode version */
-			new_rev = read_microcode_rev();
-
-#if !defined(__ROMCC__)
-			printk(BIOS_DEBUG, "microcode: updated to revision "
-				    "0x%x date=%04x-%02x-%02x\n", new_rev,
-				    m->date & 0xffff, (m->date >> 24) & 0xff,
-				    (m->date >> 16) & 0xff);
-#endif
-			break;
-		}
-
-		if (m->total_size) {
-			c += m->total_size;
-		} else {
-#if !defined(__ROMCC__)
-			printk(BIOS_WARNING, "Microcode has no valid size field!\n");
-#endif
-			c += 2048;
-		}
-	}
-
-#if !defined(__ROMCC__) && !defined(__PRE_RAM__)
-	spin_unlock(&microcode_lock);
-#endif
-}
-
-#endif
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 852c9cdf0c..7d5bf94918 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_1067X
 	select SMP
 	select SSE2
 	select TSC_SYNC_MFENCE
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index c0e98bc353..ccfeb7feda 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,3 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
new file mode 100644
index 0000000000..3b22e70233
--- /dev/null
+++ b/src/cpu/intel/model_1067x/microcode_blob.c
@@ -0,0 +1,17 @@
+unsigned microcode_updates_1067ax[] = {
+	#include "microcode-m011067660F.h"
+	#include "microcode-m041067660F.h"
+	#include "microcode-m101067660F.h"
+	#include "microcode-m101067770A.h"
+	#include "microcode-m111067AA0B.h"
+	#include "microcode-m401067660F.h"
+	#include "microcode-m441067AA0B.h"
+	#include "microcode-m801067660F.h"
+	#include "microcode-mA01067AA0B.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 47d87dea8b..2b151a3706 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -36,24 +36,6 @@
 
 #include "chip.h"
 
-static const uint32_t microcode_updates[] = {
-	#include "microcode-m011067660F.h"
-	#include "microcode-m041067660F.h"
-	#include "microcode-m101067660F.h"
-	#include "microcode-m101067770A.h"
-	#include "microcode-m111067AA0B.h"
-	#include "microcode-m401067660F.h"
-	#include "microcode-m441067AA0B.h"
-	#include "microcode-m801067660F.h"
-	#include "microcode-mA01067AA0B.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void init_timer(void)
 {
 	/* Set the apic timer to no interrupts and periodic mode */
@@ -335,7 +317,7 @@ static void model_1067x_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index e26bf1fea5..c438008eec 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -6,6 +6,7 @@ config CPU_INTEL_MODEL_106CX
 	select SIPI_VECTOR_IN_ROM
 	select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
+	select SUPPORT_CPU_UCODE_IN_CBFS
 
 config CPU_ADDR_BITS
 	int
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 1f217fe7e3..dbc093d018 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
new file mode 100644
index 0000000000..573d41f386
--- /dev/null
+++ b/src/cpu/intel/model_106cx/microcode_blob.c
@@ -0,0 +1,15 @@
+unsigned microcode_updates_106cx[] = {
+	#include "microcode-M01106C2217.h"
+	#include "microcode-M01106CA107.h"
+	#include "microcode-M04106C2218.h"
+	#include "microcode-M04106CA107.h"
+	#include "microcode-M08106C2219.h"
+	#include "microcode-M08106CA107.h"
+	#include "microcode-M10106CA107.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index e0aa120768..0d96172827 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -31,22 +31,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 
-static const uint32_t microcode_updates[] = {
-	#include "microcode-M01106C2217.h"
-	#include "microcode-M01106CA107.h"
-	#include "microcode-M04106C2218.h"
-	#include "microcode-M04106CA107.h"
-	#include "microcode-M08106C2219.h"
-	#include "microcode-M08106CA107.h"
-	#include "microcode-M10106CA107.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 #define IA32_FEATURE_CONTROL 0x003a
 
 #define CPUID_VMX (1 << 5)
@@ -135,7 +119,7 @@ static void model_106cx_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig
index 1ef48139f6..e8f0767ce4 100644
--- a/src/cpu/intel/model_65x/Kconfig
+++ b/src/cpu/intel/model_65x/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_65X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index 50639e71b8..9298037877 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,3 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
new file mode 100644
index 0000000000..f14f317743
--- /dev/null
+++ b/src/cpu/intel/model_65x/microcode_blob.c
@@ -0,0 +1,25 @@
+unsigned microcode_updates_65x[] = {
+	#include "microcode-410-MU16522d.h"
+	#include "microcode-422-MU26530b.h"
+	#include "microcode-412-MU16530d.h"
+	#include "microcode-423-MU26522b.h"
+	#include "microcode-407-MU16522a.h"
+	#include "microcode-146-MU16502e.h"
+	#include "microcode-409-MU16522c.h"
+	#include "microcode-147-MU16502f.h"
+	#include "microcode-94-MU265019.h"
+	#include "microcode-430-MU165041.h"
+	#include "microcode-452-MU165310.h"
+	#include "microcode-434-MU165140.h"
+	#include "microcode-435-MU165141.h"
+	#include "microcode-433-MU165045.h"
+	#include "microcode-429-MU165040.h"
+	#include "microcode-436-MU165142.h"
+	#include "microcode-411-MU16530c.h"
+
+	/* Dummy terminator */
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c
index 285bacd94b..69141221eb 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -29,37 +29,10 @@
 #include <cpu/x86/cache.h>
 #include <cpu/intel/l2_cache.h>
 
-static u32 microcode_updates[] = {
-	#include "microcode-410-MU16522d.h"
-	#include "microcode-422-MU26530b.h"
-	#include "microcode-412-MU16530d.h"
-	#include "microcode-423-MU26522b.h"
-	#include "microcode-407-MU16522a.h"
-	#include "microcode-146-MU16502e.h"
-	#include "microcode-409-MU16522c.h"
-	#include "microcode-147-MU16502f.h"
-	#include "microcode-94-MU265019.h"
-	#include "microcode-430-MU165041.h"
-	#include "microcode-452-MU165310.h"
-	#include "microcode-434-MU165140.h"
-	#include "microcode-435-MU165141.h"
-	#include "microcode-433-MU165045.h"
-	#include "microcode-429-MU165040.h"
-	#include "microcode-436-MU165142.h"
-	#include "microcode-411-MU16530c.h"
-
-	/* Dummy terminator */
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_65x_init(device_t dev)
 {
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
-
+	intel_update_microcode_from_cbfs();
 	/* Initialize L2 cache */
 	p6_configure_l2_cache();
 
diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig
index b65081c4bc..74ef8d5125 100644
--- a/src/cpu/intel/model_67x/Kconfig
+++ b/src/cpu/intel/model_67x/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_67X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index 48cfc153ac..04970b0648 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,3 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
new file mode 100644
index 0000000000..78404849e2
--- /dev/null
+++ b/src/cpu/intel/model_67x/microcode_blob.c
@@ -0,0 +1,13 @@
+unsigned microcode_updates_67x[] = {
+	/* Include microcode updates here. */
+	#include "microcode-293-MU267114.h"
+	#include "microcode-530-MU16730e.h"
+	#include "microcode-531-MU26732e.h"
+	#include "microcode-539-MU167210.h"
+	#include "microcode-540-MU267238.h"
+	/* Dummy terminator */
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
index 3ebe3618b1..467d3db976 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -29,24 +29,10 @@
 #include <cpu/x86/msr.h>
 #include <cpu/intel/l2_cache.h>
 
-static const uint32_t microcode_updates[] = {
-	/* Include microcode updates here. */
-	#include "microcode-293-MU267114.h"
-	#include "microcode-530-MU16730e.h"
-	#include "microcode-531-MU26732e.h"
-	#include "microcode-539-MU167210.h"
-	#include "microcode-540-MU267238.h"
-	/* Dummy terminator */
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-	0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_67x_init(device_t cpu)
 {
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Initialize L2 cache */
 	p6_configure_l2_cache();
diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig
index f7f05f6e73..9d9983ed0c 100644
--- a/src/cpu/intel/model_68x/Kconfig
+++ b/src/cpu/intel/model_68x/Kconfig
@@ -21,3 +21,4 @@
 config CPU_INTEL_MODEL_68X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index 40bdd43aad..addee29bee 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,3 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
new file mode 100644
index 0000000000..78e2e03f44
--- /dev/null
+++ b/src/cpu/intel/model_68x/microcode_blob.c
@@ -0,0 +1,25 @@
+unsigned microcode_updates_68x[] = {
+	#include "microcode-534-MU16810d.h"
+	#include "microcode-535-MU16810e.h"
+	#include "microcode-536-MU16810f.h"
+	#include "microcode-537-MU268110.h"
+	#include "microcode-538-MU168111.h"
+	#include "microcode-550-MU168307.h"
+	#include "microcode-551-MU168308.h"
+	#include "microcode-727-MU168313.h"
+	#include "microcode-728-MU168314.h"
+	#include "microcode-729-MU268310.h"
+	#include "microcode-611-MU168607.h"
+	#include "microcode-612-MU168608.h"
+	#include "microcode-615-MU16860a.h"
+	#include "microcode-617-MU16860c.h"
+	#include "microcode-618-MU268602.h"
+	#include "microcode-662-MU168a01.h"
+	#include "microcode-691-MU168a04.h"
+	#include "microcode-692-MU168a05.h"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c
index c4bd7acfe2..4bb9b5634c 100644
--- a/src/cpu/intel/model_68x/model_68x_init.c
+++ b/src/cpu/intel/model_68x/model_68x_init.c
@@ -32,32 +32,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 
-static const uint32_t microcode_updates[] = {
-	#include "microcode-534-MU16810d.h"
-	#include "microcode-535-MU16810e.h"
-	#include "microcode-536-MU16810f.h"
-	#include "microcode-537-MU268110.h"
-	#include "microcode-538-MU168111.h"
-	#include "microcode-550-MU168307.h"
-	#include "microcode-551-MU168308.h"
-	#include "microcode-727-MU168313.h"
-	#include "microcode-728-MU168314.h"
-	#include "microcode-729-MU268310.h"
-	#include "microcode-611-MU168607.h"
-	#include "microcode-612-MU168608.h"
-	#include "microcode-615-MU16860a.h"
-	#include "microcode-617-MU16860c.h"
-	#include "microcode-618-MU268602.h"
-	#include "microcode-662-MU168a01.h"
-	#include "microcode-691-MU168a04.h"
-	#include "microcode-692-MU168a05.h"
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_68x_init(device_t cpu)
 {
 	char processor_name[49];
@@ -66,7 +40,7 @@ static void model_68x_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig
index 596763cf35..4e88979c5f 100644
--- a/src/cpu/intel/model_69x/Kconfig
+++ b/src/cpu/intel/model_69x/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_69X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index 927bfeb06d..e9d90ca871 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_69x_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
new file mode 100644
index 0000000000..4b06772387
--- /dev/null
+++ b/src/cpu/intel/model_69x/microcode_blob.c
@@ -0,0 +1,11 @@
+unsigned microcode_updates_69x[] = {
+	#include "microcode-1376-m8069547.h"
+	#include "microcode-1373-m1069507.h"
+	#include "microcode-1374-m2069507.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index cb805aec51..9ee7424eb7 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -9,18 +9,6 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 
-static uint32_t microcode_updates[] = {
-	#include "microcode-1376-m8069547.h"
-	#include "microcode-1373-m1069507.h"
-	#include "microcode-1374-m2069507.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_69x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
@@ -29,7 +17,7 @@ static void model_69x_init(device_t dev)
 	x86_mtrr_check();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Enable the local cpu apics */
 	setup_lapic();
diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig
index 10661d0d96..26b5995f68 100644
--- a/src/cpu/intel/model_6bx/Kconfig
+++ b/src/cpu/intel/model_6bx/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_6BX
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 2d33f85d2f..5f1f8949ce 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,2 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
new file mode 100644
index 0000000000..a6f9bc69c4
--- /dev/null
+++ b/src/cpu/intel/model_6bx/microcode_blob.c
@@ -0,0 +1,11 @@
+unsigned microcode_updates_6bx[] = {
+	#include "microcode-737-MU16b11c.h"
+	#include "microcode-738-MU16b11d.h"
+	#include "microcode-875-MU16b401.h"
+	#include "microcode-885-MU16b402.h"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
index b7affd9dd5..e06665a2c2 100644
--- a/src/cpu/intel/model_6bx/model_6bx_init.c
+++ b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -32,18 +32,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 
-static const uint32_t microcode_updates[] = {
-	#include "microcode-737-MU16b11c.h"
-	#include "microcode-738-MU16b11d.h"
-	#include "microcode-875-MU16b401.h"
-	#include "microcode-885-MU16b402.h"
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_6bx_init(device_t cpu)
 {
 	char processor_name[49];
@@ -52,7 +40,7 @@ static void model_6bx_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig
index 5e70f59117..546d9ece2e 100644
--- a/src/cpu/intel/model_6dx/Kconfig
+++ b/src/cpu/intel/model_6dx/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_6DX
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index cc88a2c513..4731de3858 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_6dx_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
new file mode 100644
index 0000000000..52489e4c7c
--- /dev/null
+++ b/src/cpu/intel/model_6dx/microcode_blob.c
@@ -0,0 +1,9 @@
+unsigned microcode_updates_6dx[] = {
+	#include "microcode-1355-m206d618.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 19b351dd1c..06236a3b3b 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -9,16 +9,6 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 
-static uint32_t microcode_updates[] = {
-	#include "microcode-1355-m206d618.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_6dx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
@@ -27,7 +17,7 @@ static void model_6dx_init(device_t dev)
 	x86_mtrr_check();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Enable the local cpu apics */
 	setup_lapic();
diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig
index e2b1986132..8187838163 100644
--- a/src/cpu/intel/model_6ex/Kconfig
+++ b/src/cpu/intel/model_6ex/Kconfig
@@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6EX
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index b515c4f69a..6d943023c8 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,3 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
new file mode 100644
index 0000000000..0798316d40
--- /dev/null
+++ b/src/cpu/intel/model_6ex/microcode_blob.c
@@ -0,0 +1,10 @@
+unsigned microcode_updates_6ex[] = {
+	#include "microcode-1624-m206e839.h"
+	#include "microcode-1729-m206ec54.h"
+	#include "microcode-1869-m806ec59.h"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index e9c63da16f..4dc642a61e 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -33,16 +33,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 
-static const uint32_t microcode_updates[] = {
-	#include "microcode-1624-m206e839.h"
-	#include "microcode-1729-m206ec54.h"
-	#include "microcode-1869-m806ec59.h"
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
 
 #define IA32_FEATURE_CONTROL 0x003a
 
@@ -160,7 +150,7 @@ static void model_6ex_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
index 4517f17fa6..3335a26211 100644
--- a/src/cpu/intel/model_6fx/Kconfig
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6FX
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index b75cde3dce..6a1bb51cf5 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,2 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
new file mode 100644
index 0000000000..f17613b47a
--- /dev/null
+++ b/src/cpu/intel/model_6fx/microcode_blob.c
@@ -0,0 +1,26 @@
+unsigned microcode_updates_6fx[] = {
+	#include "microcode-m016fbBA.h"
+	#include "microcode-m046fbBC.h"
+	#include "microcode-m086fbBB.h"
+	#include "microcode-m106f76a.h"
+	#include "microcode-m106fbBA.h"
+	#include "microcode-m16f25d.h"
+	#include "microcode-m16f6d0.h"
+	#include "microcode-m16fda4.h"
+	#include "microcode-m206f25c.h"
+	#include "microcode-m206f6d1.h"
+	#include "microcode-m206fbBA.h"
+	#include "microcode-m206fda4.h"
+	#include "microcode-m406f76b.h"
+	#include "microcode-m406fbBC.h"
+	#include "microcode-m46f6d2.h"
+	#include "microcode-m806fa95.h"
+	#include "microcode-m806fbBA.h"
+	#include "microcode-m806fda4.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index faf1277bd2..39aa8e9720 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -33,33 +33,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 
-static const uint32_t microcode_updates[] = {
-	#include "microcode-m016fbBA.h"
-	#include "microcode-m046fbBC.h"
-	#include "microcode-m086fbBB.h"
-	#include "microcode-m106f76a.h"
-	#include "microcode-m106fbBA.h"
-	#include "microcode-m16f25d.h"
-	#include "microcode-m16f6d0.h"
-	#include "microcode-m16fda4.h"
-	#include "microcode-m206f25c.h"
-	#include "microcode-m206f6d1.h"
-	#include "microcode-m206fbBA.h"
-	#include "microcode-m206fda4.h"
-	#include "microcode-m406f76b.h"
-	#include "microcode-m406fbBC.h"
-	#include "microcode-m46f6d2.h"
-	#include "microcode-m806fa95.h"
-	#include "microcode-m806fbBA.h"
-	#include "microcode-m806fda4.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 #define IA32_FEATURE_CONTROL 0x003a
 
 #define CPUID_VMX (1 << 5)
@@ -197,7 +170,7 @@ static void model_6fx_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig
index 96c7040706..b572385b4f 100644
--- a/src/cpu/intel/model_6xx/Kconfig
+++ b/src/cpu/intel/model_6xx/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_6XX
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 5fdd71c55b..0c41cf2487 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_6xx_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
new file mode 100644
index 0000000000..8a7ef26c93
--- /dev/null
+++ b/src/cpu/intel/model_6xx/microcode_blob.c
@@ -0,0 +1,33 @@
+unsigned microcode_updates_6xx[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+
+#include "microcode-99-B_c6_612.h"
+#include "microcode-43-B_c6_617.h"
+#include "microcode-51-B_c6_616.h"
+#include "microcode-153-d2_619.h"
+
+#include "microcode-308-MU163336.h"
+#include "microcode-309-MU163437.h"
+
+#include "microcode-358-MU166d05.h"
+#include "microcode-359-MU166d06.h"
+#include "microcode-386-MU16600a.h"
+#include "microcode-398-MU166503.h"
+#include "microcode-399-MU166a0b.h"
+#include "microcode-400-MU166a0c.h"
+#include "microcode-401-MU166a0d.h"
+#include "microcode-402-MU166d07.h"
+
+#include "microcode-566-mu26a003.h"
+#include "microcode-588-mu26a101.h"
+#include "microcode-620-MU26a401.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 5724add4e8..e81f9aebe8 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -9,40 +9,6 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 
-static uint32_t microcode_updates[] = {
-	/* WARNING - Intel has a new data structure that has variable length
-	 * microcode update lengths.  They are encoded in int 8 and 9.  A
-	 * dummy header of nulls must terminate the list.
-	 */
-
-#include "microcode-99-B_c6_612.h"
-#include "microcode-43-B_c6_617.h"
-#include "microcode-51-B_c6_616.h"
-#include "microcode-153-d2_619.h"
-
-#include "microcode-308-MU163336.h"
-#include "microcode-309-MU163437.h"
-
-#include "microcode-358-MU166d05.h"
-#include "microcode-359-MU166d06.h"
-#include "microcode-386-MU16600a.h"
-#include "microcode-398-MU166503.h"
-#include "microcode-399-MU166a0b.h"
-#include "microcode-400-MU166a0c.h"
-#include "microcode-401-MU166a0d.h"
-#include "microcode-402-MU166d07.h"
-
-#include "microcode-566-mu26a003.h"
-#include "microcode-588-mu26a101.h"
-#include "microcode-620-MU26a401.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_6xx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
@@ -51,7 +17,7 @@ static void model_6xx_init(device_t dev)
 	x86_mtrr_check();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Enable the local cpu apics */
 	setup_lapic();
diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig
index 9dd7fd0bdc..06165890e1 100644
--- a/src/cpu/intel/model_f0x/Kconfig
+++ b/src/cpu/intel/model_f0x/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F0X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 79ea2a0632..6c16419947 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_f0x_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
new file mode 100644
index 0000000000..079a2cb390
--- /dev/null
+++ b/src/cpu/intel/model_f0x/microcode_blob.c
@@ -0,0 +1,14 @@
+/* 256KB cache */
+unsigned microcode_updates_f0x[] = {
+	#include "microcode-678-2f0708.h"
+	#include "microcode-965-m01f0a13.h"
+	#include "microcode-983-m02f0a15.h"
+	#include "microcode-964-m01f0712.h"
+	#include "microcode-966-m04f0a14.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index ed12b6edfd..8d8118224e 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -9,21 +9,6 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 
-/* 256KB cache */
-static uint32_t microcode_updates[] = {
-	#include "microcode-678-2f0708.h"
-	#include "microcode-965-m01f0a13.h"
-	#include "microcode-983-m02f0a15.h"
-	#include "microcode-964-m01f0712.h"
-	#include "microcode-966-m04f0a14.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_f0x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
@@ -32,7 +17,7 @@ static void model_f0x_init(device_t dev)
 	x86_mtrr_check();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Enable the local cpu apics */
 	setup_lapic();
diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig
index ea75857949..fd649201f5 100644
--- a/src/cpu/intel/model_f1x/Kconfig
+++ b/src/cpu/intel/model_f1x/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F1X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index 6449ae90ec..c7062346fa 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_f1x_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
new file mode 100644
index 0000000000..308402c5e1
--- /dev/null
+++ b/src/cpu/intel/model_f1x/microcode_blob.c
@@ -0,0 +1,17 @@
+/* 256KB cache */
+unsigned microcode_updates_f1x[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+	#include "microcode-1068-m01f122d.h"
+	#include "microcode-1069-m04f122e.h"
+	#include "microcode-1070-m02f122f.h"
+	#include "microcode-1072-m04f1305.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index feb841050c..b294c6193a 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -9,24 +9,6 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 
-/* 256KB cache */
-static uint32_t microcode_updates[] = {
-	/* WARNING - Intel has a new data structure that has variable length
-	 * microcode update lengths.  They are encoded in int 8 and 9.  A
-	 * dummy header of nulls must terminate the list.
-	 */
-	#include "microcode-1068-m01f122d.h"
-	#include "microcode-1069-m04f122e.h"
-	#include "microcode-1070-m02f122f.h"
-	#include "microcode-1072-m04f1305.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_f1x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
@@ -35,7 +17,7 @@ static void model_f1x_init(device_t dev)
 	x86_mtrr_check();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Enable the local cpu apics */
 	setup_lapic();
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
index 50cac7937c..8483d332f4 100644
--- a/src/cpu/intel/model_f2x/Kconfig
+++ b/src/cpu/intel/model_f2x/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F2X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 9b366d6e8e..3360611b31 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_f2x_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
new file mode 100644
index 0000000000..e8c9302a37
--- /dev/null
+++ b/src/cpu/intel/model_f2x/microcode_blob.c
@@ -0,0 +1,33 @@
+/* 512KB cache */
+unsigned microcode_updates_f2x[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+
+	/* Old microcode file not present in Intel's microcode.dat. */
+#include "microcode_m02f2203.h"
+
+	/* files from Intel's microcode.dat */
+#include "microcode-1343-m04f252b.h"
+#include "microcode-1346-m10f252c.h"
+#include "microcode-1338-m02f292d.h"
+#include "microcode-1340-m08f292f.h"
+#include "microcode-1107-m10f2421.h"
+#include "microcode-1339-m04f292e.h"
+#include "microcode-1105-m08f2420.h"
+#include "microcode-1336-m02f2610.h"
+#include "microcode-1101-m02f2738.h"
+#include "microcode-1100-m04f2737.h"
+#include "microcode-1341-m01f2529.h"
+#include "microcode-1102-m08f2739.h"
+#include "microcode-1104-m04f241e.h"
+#include "microcode-1342-m02f252a.h"
+#include "microcode-1106-m02f241f.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index 8fd8abc7bf..9e8fbfc84f 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -10,40 +10,6 @@
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 
-/* 512KB cache */
-static uint32_t microcode_updates[] = {
-	/* WARNING - Intel has a new data structure that has variable length
-	 * microcode update lengths.  They are encoded in int 8 and 9.  A
-	 * dummy header of nulls must terminate the list.
-	 */
-
-	/* Old microcode file not present in Intel's microcode.dat. */
-#include "microcode_m02f2203.h"
-
-	/* files from Intel's microcode.dat */
-#include "microcode-1343-m04f252b.h"
-#include "microcode-1346-m10f252c.h"
-#include "microcode-1338-m02f292d.h"
-#include "microcode-1340-m08f292f.h"
-#include "microcode-1107-m10f2421.h"
-#include "microcode-1339-m04f292e.h"
-#include "microcode-1105-m08f2420.h"
-#include "microcode-1336-m02f2610.h"
-#include "microcode-1101-m02f2738.h"
-#include "microcode-1100-m04f2737.h"
-#include "microcode-1341-m01f2529.h"
-#include "microcode-1102-m08f2739.h"
-#include "microcode-1104-m04f241e.h"
-#include "microcode-1342-m02f252a.h"
-#include "microcode-1106-m02f241f.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_f2x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
@@ -55,7 +21,7 @@ static void model_f2x_init(device_t cpu)
 		x86_mtrr_check();
 
 		/* Update the microcode */
-		intel_update_microcode(microcode_updates);
+		intel_update_microcode_from_cbfs();
 	}
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
index 4cfca83dc6..8ae2dcff29 100644
--- a/src/cpu/intel/model_f3x/Kconfig
+++ b/src/cpu/intel/model_f3x/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F3X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index cf8f918514..ebd47cfcf8 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_f3x_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
new file mode 100644
index 0000000000..0bd2a5b4b0
--- /dev/null
+++ b/src/cpu/intel/model_f3x/microcode_blob.c
@@ -0,0 +1,16 @@
+unsigned microcode_updates_f3x[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+
+#include "microcode-1290-m0df320a.h"
+#include "microcode-1467-m0df330c.h"
+#include "microcode-1468-m1df3417.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index 2504ba9423..5752347943 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -10,23 +10,6 @@
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 
-static uint32_t microcode_updates[] = {
-	/* WARNING - Intel has a new data structure that has variable length
-	 * microcode update lengths.  They are encoded in int 8 and 9.  A
-	 * dummy header of nulls must terminate the list.
-	 */
-
-#include "microcode-1290-m0df320a.h"
-#include "microcode-1467-m0df330c.h"
-#include "microcode-1468-m1df3417.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_f3x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
@@ -38,7 +21,7 @@ static void model_f3x_init(device_t cpu)
 		x86_mtrr_check();
 
 		/* Update the microcode */
-		intel_update_microcode(microcode_updates);
+		intel_update_microcode_from_cbfs();
 	}
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig
index 97c909a0ae..c21a2743bf 100644
--- a/src/cpu/intel/model_f4x/Kconfig
+++ b/src/cpu/intel/model_f4x/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F4X
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index ac99095b53..6ade9f3749 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_f4x_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
new file mode 100644
index 0000000000..4f1147cc50
--- /dev/null
+++ b/src/cpu/intel/model_f4x/microcode_blob.c
@@ -0,0 +1,24 @@
+unsigned microcode_updates_f4x[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+
+	#include "microcode-1735-m01f480c.h"
+	#include "microcode-1460-m9df4305.h"
+	#include "microcode-2492-m02f480e.h"
+	#include "microcode-1470-m9df4703.h"
+	#include "microcode-1521-m5ff4807.h"
+	#include "microcode-1466-m02f4116.h"
+	#include "microcode-1469-m9df4406.h"
+	#include "microcode-1471-mbdf4117.h"
+	#include "microcode-1637-m5cf4a04.h"
+	#include "microcode-1462-mbdf4903.h"
+	#include "microcode-1498-m5df4a02.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index f3f0b2af0f..80d7dc8056 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -10,31 +10,6 @@
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 
-static uint32_t microcode_updates[] = {
-	/* WARNING - Intel has a new data structure that has variable length
-	 * microcode update lengths.  They are encoded in int 8 and 9.  A
-	 * dummy header of nulls must terminate the list.
-	 */
-
-	#include "microcode-1735-m01f480c.h"
-	#include "microcode-1460-m9df4305.h"
-	#include "microcode-2492-m02f480e.h"
-	#include "microcode-1470-m9df4703.h"
-	#include "microcode-1521-m5ff4807.h"
-	#include "microcode-1466-m02f4116.h"
-	#include "microcode-1469-m9df4406.h"
-	#include "microcode-1471-mbdf4117.h"
-	#include "microcode-1637-m5cf4a04.h"
-	#include "microcode-1462-mbdf4903.h"
-	#include "microcode-1498-m5df4a02.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_f4x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
@@ -46,7 +21,7 @@ static void model_f4x_init(device_t cpu)
 		x86_mtrr_check();
 
 		/* Update the microcode */
-		intel_update_microcode(microcode_updates);
+		intel_update_microcode_from_cbfs();
 	}
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 92775aadfd..e3e6fb2380 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -19,10 +19,20 @@
 
 config CPU_INTEL_SLOT_1
 	bool
+
+if CPU_INTEL_SLOT_1
+
+config SLOT_SPECIFIC_OPTIONS # dummy
+	def_bool y
 	select CACHE_AS_RAM
+	select CPU_INTEL_MODEL_65X
+	select CPU_INTEL_MODEL_67X
+	select CPU_INTEL_MODEL_68X
+	select CPU_INTEL_MODEL_6BX
+	select CPU_INTEL_MODEL_6XX
 
 config DCACHE_RAM_SIZE
 	hex
 	default 0x01000
-	depends on CPU_INTEL_SLOT_1
 
+endif
diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig
index 7ab293374a..c8a4b59ca5 100644
--- a/src/cpu/intel/socket_PGA370/Kconfig
+++ b/src/cpu/intel/socket_PGA370/Kconfig
@@ -19,6 +19,7 @@
 
 config CPU_INTEL_SOCKET_PGA370
 	bool
+	select CPU_INTEL_MODEL_6XX
 	select MMX
 	select UDELAY_TSC
 	select CACHE_AS_RAM