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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-10-01 12:52:52 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-10-01 12:52:52 +0000 |
| commit | 2ee6779a64922af755a35ce70f85f2d67b488557 (patch) | |
| tree | 4ae6d7310d71fa29baab3e937cfcd9bb408db5a6 /src/cpu | |
| parent | dc65196f8f18c28085d40ccbeb45bba3bfe28294 (diff) | |
| download | coreboot-2ee6779a64922af755a35ce70f85f2d67b488557.tar.xz | |
The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 8 | ||||
| -rw-r--r-- | src/cpu/amd/sc520/sc520.c | 2 | ||||
| -rw-r--r-- | src/cpu/emulation/qemu-x86/northbridge.c | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 63859b004b..2b08b61791 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -522,7 +522,7 @@ static void setup_remote_node(u8 node) printk_debug("setup_remote_node: %02x", node); /* copy the default resource map from node 0 */ - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { + for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { u32 value; u16 reg; reg = pci_reg[i]; @@ -852,7 +852,7 @@ void cpuSetAMDMSR(void) revision = mctGetLogicalCPUID(0xFF); platform = get_platform_type(); - for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) { if ((fam10_msr_default[i].revision & revision) && (fam10_msr_default[i].platform & platform)) { msr = rdmsr(fam10_msr_default[i].msr); @@ -889,7 +889,7 @@ void cpuSetAMDPCI(u8 node) AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */ - for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { if ((fam10_pci_default[i].revision & revision) && (fam10_pci_default[i].platform & platform)) { val = pci_read_config32(NODE_PCI(node, @@ -903,7 +903,7 @@ void cpuSetAMDPCI(u8 node) } } - for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { if ((fam10_htphy_default[i].revision & revision) && (fam10_htphy_default[i].platform & platform)) { /* HT Phy settings either apply to both sublinks or have diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 2ec3f5a47e..fef3c7f0ab 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -151,7 +151,7 @@ static void pci_domain_set_resources(device_t dev) // int i; int idx; #if 0 - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. diff --git a/src/cpu/emulation/qemu-x86/northbridge.c b/src/cpu/emulation/qemu-x86/northbridge.c index ada22fe982..f005fab852 100644 --- a/src/cpu/emulation/qemu-x86/northbridge.c +++ b/src/cpu/emulation/qemu-x86/northbridge.c @@ -80,7 +80,7 @@ static void pci_domain_set_resources(device_t dev) unsigned char rambits; int i, idx; - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. |