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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 10:49:11 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:49:20 +0000 |
| commit | 4ff675ebd071755dcb278836a16ae1ea10c63e50 (patch) | |
| tree | 6e9f4f383b3e82049eaaf29302ba79860ce78049 /src/cpu | |
| parent | aa7cf5597b0f4d59c5d7fe42a8b5130852056bff (diff) | |
| download | coreboot-4ff675ebd071755dcb278836a16ae1ea10c63e50.tar.xz | |
nb/intel/x4x: Switch to POSTCAR_STAGE
Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/socket_LGA775/Makefile.inc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 7ff2f33f3f..ceb084c900 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,10 +13,7 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -else cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S postcar-y += ../car/p4-netburst/exit_car.S -endif + romstage-y += ../car/romstage.c |