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authorDavid Hendricks <dhendrix@chromium.org>2013-08-08 16:16:40 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 22:46:28 +0100
commit5f6ffbab1b67ed34aac4b85ae9e64dbd08e373f2 (patch)
tree2d1286cdbdcdf40ec79541057b8fc668b50e0492 /src/cpu
parentbd56bf0dcff59d38066715438a9350f50136fcc3 (diff)
downloadcoreboot-5f6ffbab1b67ed34aac4b85ae9e64dbd08e373f2.tar.xz
exynos5420: add CPLL and DPLL to the known list of PLLs
This patch adds CPLL and DPLL to the known list of PLLs. This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af Reviewed-on: https://gerrit.chromium.org/gerrit/65282 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4461 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/samsung/exynos5420/clk.h2
-rw-r--r--src/cpu/samsung/exynos5420/clock.c6
2 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h
index a4e538d370..b37c076582 100644
--- a/src/cpu/samsung/exynos5420/clk.h
+++ b/src/cpu/samsung/exynos5420/clk.h
@@ -33,6 +33,8 @@ enum periph_id;
#define BPLL 5
#define RPLL 6
#define SPLL 7
+#define CPLL 8
+#define DPLL 9
enum pll_src_bit {
EXYNOS_SRC_CPLL = 1,
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index ed5b102d94..b8e27ff5f0 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -103,6 +103,12 @@ unsigned long get_pll_clk(int pllreg)
case SPLL:
r = readl(&clk->spll_con0);
break;
+ case CPLL:
+ r = readl(&clk->cpll_con0);
+ break;
+ case DPLL:
+ r = readl(&clk->dpll_con0);
+ break;
default:
printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
return 0;