Drop \r\n and \n\r as both print_XXX and printk now do this internally.

Only some assembler files still have \r\n ... Can we move that part to C
completely?

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 70 insertions, 70 deletions

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 939990997c..b8a7285b89 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -5,7 +5,7 @@
 
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
-	printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
+	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 }
 
 /* from linux kernel 2.6.32 asm/string_32.h */
@@ -86,10 +86,10 @@ static void post_cache_as_ram(void)
 	/* We can put data to stack again */
 
 	/* only global variable sysinfo in cache need to be offset */
-	print_debug("Done\r\n");
+	print_debug("Done\n");
 	print_debug_pcar("testx = ", testx);
 
-	print_debug("Disabling cache as ram now \r\n");
+	print_debug("Disabling cache as ram now \n");
 	disable_cache_as_ram_bsp();
 
 	print_debug("Clearing initial memory region: ");
@@ -99,7 +99,7 @@ static void post_cache_as_ram(void)
 #else
 	memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
 #endif
-	print_debug("Done\r\n");
+	print_debug("Done\n");
 
 //	dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
@@ -115,5 +115,5 @@ static void post_cache_as_ram(void)
 	copy_and_run();
 	/* We will not return */
 
-	print_debug("should not be here -\r\n");
+	print_debug("should not be here -\n");
 }
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index 3a56fdd1c3..42d96c509a 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -109,7 +109,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n");
+		printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
 		enable_apic_ext_id(nodes);
 	}
 	
diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c
index 59cb5460d2..2b23e11c1d 100644
--- a/src/cpu/amd/model_fxx/fidvid.c
+++ b/src/cpu/amd/model_fxx/fidvid.c
@@ -15,21 +15,21 @@
 static inline void print_debug_fv(const char *str, unsigned val)
 {
 #if K8_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%x\r\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_8(const char *str, unsigned val)
 {
 #if K8_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%02x\r\n", str, val);
+		printk(BIOS_DEBUG, "%s%02x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
 {
 #if K8_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%x%x\r\n", str, val, val2);
+		printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
 #endif
 }
 
@@ -131,7 +131,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
 	apicidx = lapicid();
 
 	if (apicid != apicidx) {
-		printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
+		printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx);
 		return fidvid;
 	}
 
@@ -328,10 +328,10 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
 
 	if (showmessage) {
 		if (vid_new != vid_cur) {
-			print_err("set vid failed for apicid ="); print_err_hex8(apicidx);  print_err("\r\n");
+			print_err("set vid failed for apicid ="); print_err_hex8(apicidx);  print_err("\n");
 		}
 		if (fid_new != fid_cur) {
-			print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n");
+			print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
 		}
 	}
 
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 847a8a7fa6..151eb6f01c 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -16,7 +16,7 @@
 
 static inline void print_initcpu8 (const char *strval, unsigned val)
 {
-        printk(BIOS_DEBUG, "%s%02x\r\n", strval, val);
+        printk(BIOS_DEBUG, "%s%02x\n", strval, val);
 }
 
 static inline void print_initcpu8_nocr (const char *strval, unsigned val)
@@ -27,12 +27,12 @@ static inline void print_initcpu8_nocr (const char *strval, unsigned val)
 
 static inline void print_initcpu16 (const char *strval, unsigned val)
 {
-        printk(BIOS_DEBUG, "%s%04x\r\n", strval, val);
+        printk(BIOS_DEBUG, "%s%04x\n", strval, val);
 }
 
 static inline void print_initcpu(const char *strval, unsigned val)
 {
-        printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
+        printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 }
 
 typedef void (*process_ap_t)(unsigned apicid, void *gp);
@@ -155,7 +155,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid);
 
 static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
 {
-                printk(BIOS_DEBUG, "%s --- {  APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
+                printk(BIOS_DEBUG, "%s --- {  APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
 }
 
 
@@ -201,7 +201,7 @@ static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other t
 {
         print_debug("started ap apicid: ");
         for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
-        print_debug("\r\n");
+        print_debug("\n");
 }
 
 static void allow_all_aps_stop(unsigned bsp_apicid)
@@ -286,8 +286,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
 #endif
 
                 if (cpu_init_detectedx) {
-                        print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from ");
-                        print_debug("\r\nIssuing SOFT_RESET...\r\n");
+                        print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from ");
+                        print_debug("\nIssuing SOFT_RESET...\n");
                         soft_reset();
                 }
 
@@ -351,7 +351,7 @@ static void wait_all_core0_started(void)
                 while(!is_core0_started(i)) {}
                 print_initcpu8_nocr(" ", i);
         }
-        print_debug("\r\n");
+        print_debug("\n");
 
 }
 
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index ac8b7b1f66..a80c0922c0 100644
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -209,9 +209,9 @@ void SetDelayControl(void)
 	print_debug_hex32(msr.hi);
 	print_debug(" and lo ");
 	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
+	print_debug("\n");
 	wrmsr(GLCP_DELAY_CONTROLS, msr);
-	print_debug("SetDelayControl done\r\n");
+	print_debug("SetDelayControl done\n");
 	return;
 }
 
@@ -225,7 +225,7 @@ void cpuRegInit(void)
 
 	/* Castle 2.0 BTM periodic sync period. */
 	/*      [40:37] 1 sync record per 256 bytes */
-	print_debug("Castle 2.0 BTM periodic sync period.\r\n");
+	print_debug("Castle 2.0 BTM periodic sync period.\n");
 	msrnum = CPU_PF_CONF;
 	msr = rdmsr(msrnum);
 	msr.hi |= (0x8 << 5);
@@ -235,7 +235,7 @@ void cpuRegInit(void)
 	 * LX performance setting.
 	 * Enable Quack for fewer re-RAS on the MC
 	 */
-	print_debug("Enable Quack for fewer re-RAS on the MC\r\n");
+	print_debug("Enable Quack for fewer re-RAS on the MC\n");
 	msrnum = GLIU0_ARB;
 	msr = rdmsr(msrnum);
 	msr.hi &= ~ARB_UPPER_DACK_EN_SET;
@@ -251,25 +251,25 @@ void cpuRegInit(void)
 	/* GLIU port active enable, limit south pole masters 
 	 * (AES and PCI) to one outstanding transaction. 
 	 */
-	print_debug(" GLIU port active enable\r\n");
+	print_debug(" GLIU port active enable\n");
 	msrnum = GLIU1_PORT_ACTIVE;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~0x880;
 	wrmsr(msrnum, msr);
 
 	/* Set the Delay Control in GLCP */
-	print_debug("Set the Delay Control in GLCP\r\n");
+	print_debug("Set the Delay Control in GLCP\n");
 	SetDelayControl();
 
 	/*  Enable RSDC */
-	print_debug("Enable RSDC\r\n");
+	print_debug("Enable RSDC\n");
 	msrnum = CPU_AC_SMM_CTL;
 	msr = rdmsr(msrnum);
 	msr.lo |= SMM_INST_EN_SET;
 	wrmsr(msrnum, msr);
 
 	/* FPU imprecise exceptions bit */
-	print_debug("FPU imprecise exceptions bit\r\n");
+	print_debug("FPU imprecise exceptions bit\n");
 	msrnum = CPU_FPU_MSR_MODE;
 	msr = rdmsr(msrnum);
 	msr.lo |= FPU_IE_SET;
@@ -277,14 +277,14 @@ void cpuRegInit(void)
 
 	/* Power Savers (Do after BIST) */
 	/* Enable Suspend on HLT & PAUSE instructions */
-	print_debug("Enable Suspend on HLT & PAUSE instructions\r\n");
+	print_debug("Enable Suspend on HLT & PAUSE instructions\n");
 	msrnum = CPU_XC_CONFIG;
 	msr = rdmsr(msrnum);
 	msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
 	wrmsr(msrnum, msr);
 
 	/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
-	print_debug("Enable SUSP and allow TSC to run in Suspend\r\n");
+	print_debug("Enable SUSP and allow TSC to run in Suspend\n");
 	msrnum = CPU_BC_CONF_0;
 	msr = rdmsr(msrnum);
 	msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
@@ -302,10 +302,10 @@ void cpuRegInit(void)
 #endif
 
 	/* Setup throttling delays to proper mode if it is ever enabled. */
-	print_debug("Setup throttling delays to proper mode\r\n");
+	print_debug("Setup throttling delays to proper mode\n");
 	msrnum = GLCP_TH_OD;
 	msr.hi = 0;
 	msr.lo = 0x00000603C;
 	wrmsr(msrnum, msr);
-	print_debug("Done cpuRegInit\r\n");
+	print_debug("Done cpuRegInit\n");
 }
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index 4f5c68efd5..48917e3d1d 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -114,7 +114,7 @@ u32 get_apicid_base(u32 ioapic_num)
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
+		printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n");
 		enable_apic_ext_id(sysconf.nodes);
 	}
 
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index f52e8fe622..711614a5b8 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -248,14 +248,14 @@ udelay(int microseconds) {
 
 
 static void dumpram(void){
-  print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n");
-  print_err("mctl "); print_err_hex8(*drcmctl); print_err("\r\n");
-  print_err("cfg "); print_err_hex8(*drccfg); print_err("\r\n");
-
-  print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\r\n");
-  print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\r\n");
-  print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\r\n");
-  print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\r\n");
+  print_err("ctl "); print_err_hex8(*drcctl); print_err("\n");
+  print_err("mctl "); print_err_hex8(*drcmctl); print_err("\n");
+  print_err("cfg "); print_err_hex8(*drccfg); print_err("\n");
+
+  print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\n");
+  print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\n");
+  print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\n");
+  print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n");
 }
 
 /* there is a lot of silliness in the amd code, and it is 
@@ -311,11 +311,11 @@ int sizemem(void)
 	print_err("NOP\n");
 	/* 100? 200? */
 	udelay(100);
-	print_err("after sc520_udelay\r\n");
+	print_err("after sc520_udelay\n");
 
 	/* issue all banks precharge */
 	*drcctl=0x02;
-	print_err("set *drcctl to 2 \r\n");
+	print_err("set *drcctl to 2 \n");
 	dummy_write();
 	print_err("PRE\n");
 
@@ -334,7 +334,7 @@ int sizemem(void)
 	*drcctl=0x04;
 	for (i=0; i<8; i++) /* refresh 8 times */{
 		dummy_write();
-		print_err("dummy write\r\n");
+		print_err("dummy write\n");
 	}
 	print_err("8 dummy writes\n");
 
@@ -342,18 +342,18 @@ int sizemem(void)
 	*drcctl=0x00;
 	print_err("normal\n");
 
-	print_err("HI done normal\r\n");
+	print_err("HI done normal\n");
 
 	print_err("sizemem\n");
 	for(bank = 3; bank >= 0; bank--) {
-	  print_err("Try to assign to l\r\n");
+	  print_err("Try to assign to l\n");
 	  *lp = 0xdeadbeef;
-	  print_err("assigned l ... \r\n");
+	  print_err("assigned l ... \n");
 	  if (*lp != 0xdeadbeef) {
 	    print_err(" no memory at bank "); 
 	    // print_err_hex8(bank); 
 	    //   print_err(" value "); print_err_hex32(*lp);
-	    print_err("\r\n"); 
+	    print_err("\n"); 
 	    //	    continue;
 	  }
 	  *drcctl = 2;
@@ -362,7 +362,7 @@ int sizemem(void)
 	  l = *drcbendadr;
 	  l >>= 8; 
 	  *drcbendadr = l;
-	  print_err("loop around\r\n");
+	  print_err("loop around\n");
 	  *drcctl = 0;
 	  dummy_write();
 	}
@@ -386,11 +386,11 @@ int sizemem(void)
 	print_err("NOP\n");
 	/* 100? 200? */
 	//sc520_udelay(100);
-	print_err("after sc520_udelay\r\n");
+	print_err("after sc520_udelay\n");
 
 	/* issue all banks precharge */
 	*drcctl=0x02;
-	print_err("set *drcctl to 2 \r\n");
+	print_err("set *drcctl to 2 \n");
 	dummy_write();
 	print_err("PRE\n");
 
@@ -409,7 +409,7 @@ int sizemem(void)
 	*drcctl=0x04;
 	for (i=0; i<8; i++) /* refresh 8 times */{
 		dummy_write();
-		print_err("dummy write\r\n");
+		print_err("dummy write\n");
 	}
 	print_err("8 dummy writes\n");
 
@@ -417,7 +417,7 @@ int sizemem(void)
 	*drcctl=0x00;
 	print_err("normal\n");
 
-	print_err("HI done normal\r\n");
+	print_err("HI done normal\n");
 	bank = 3;
 
 
@@ -558,7 +558,7 @@ print_err("4b\n");
 	al -= i&3;
 	*drcbendaddr = rows >> al;
 	print_err("computed ending_adr = "); print_err_hex8(ending_adr); 
-	print_err("\r\n");
+	print_err("\n");
 	
 */
 bad_reinit:
@@ -592,7 +592,7 @@ bad_reinit:
 	return bank;
 	
 bad_ram:
-	print_info("bad ram!\r\n");
+	print_info("bad ram!\n");
 	/* you are here because the read-after-write failed, 
 	 * in most cases because: no ram in that bank! 
 	 * set badbank to 1 and go to reinit
@@ -600,7 +600,7 @@ bad_ram:
 	ending_adr = 0;
 	goto bad_reinit;
 	while(1)
-	print_err("DONE NEXTBANK\r\n");
+	print_err("DONE NEXTBANK\n");
 #endif
 }	
 
@@ -628,27 +628,27 @@ int staticmem(void)
 	/* two autorefreshes */
 	*drcctl = 4;
 	*zero = 0;
-	print_debug("one zero out on refresh\r\n");
+	print_debug("one zero out on refresh\n");
 	*zero = 0;
-	print_debug("two zero out on refresh\r\n");
+	print_debug("two zero out on refresh\n");
 
 	/* load mode register */
 	*drcctl = 3;
 	*zero = 0;
-	print_debug("DONE the load mode reg\r\n");
+	print_debug("DONE the load mode reg\n");
 	
 	/* normal mode */
 	*drcctl = 0x0;
 	*zero = 0;
-	print_debug("DONE one last write and then turn on refresh etc\r\n");
+	print_debug("DONE one last write and then turn on refresh etc\n");
 	*drcctl = 0x18;
 	*zero = 0;
-	print_debug("DONE the normal\r\n");
+	print_debug("DONE the normal\n");
 	*zero = 0xdeadbeef;
 	if (*zero != 0xdeadbeef) 
-	  print_debug("NO LUCK\r\n");
+	  print_debug("NO LUCK\n");
 	else
-	  print_debug("did a store and load ...\r\n");
+	  print_debug("did a store and load ...\n");
 	//print_err_hex32(*zero);
-	//	print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n");
+	//	print_err(" zero is now "); print_err_hex32(*zero); print_err("\n");
 }
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index a02323dedf..22c3a11503 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -82,7 +82,7 @@ void intel_update_microcode(const void *microcode_updates)
 	print_debug_hex32(pf);
 	print_debug(" rev = 0x");
 	print_debug_hex32(rev);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	m = microcode_updates;
 	for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
@@ -99,7 +99,7 @@ void intel_update_microcode(const void *microcode_updates)
 			print_debug_hex32(new_rev);
 			print_debug(" from revision ");
 			print_debug_hex32(rev);
-			print_debug("\r\n");
+			print_debug("\n");
 			break;
 		}
 		if (m->total_size) {
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
index fa7ab74bbc..40269ba5b3 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
@@ -40,10 +40,10 @@ void stage1_main(unsigned long bist)
         	        "movl   %%esp, %0\n\t"
 	                : "=a" (v_esp)
 	        );
-	        printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp);
+	        printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
         }
 
-        printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset);
+        printk(BIOS_SPEW, "cpu_reset = %08x\n",cpu_reset);
 
 	if(cpu_reset == 0) {
 	        print_spew("Clearing initial memory region: ");
@@ -83,12 +83,12 @@ void stage1_main(unsigned long bist)
 #ifdef CONFIG_DEACTIVATE_CAR
 		print_debug("Deactivating CAR");
 #include CONFIG_DEACTIVATE_CAR_FILE
-		print_debug(" - Done.\r\n");
+		print_debug(" - Done.\n");
 #endif
 		/* Copy and execute coreboot_ram */
 		copy_and_run(new_cpu_reset);
 		/* We will not return */
 	}
 
-	print_debug("sorry. parachute did not open.\r\n");
+	print_debug("sorry. parachute did not open.\n");
 }