diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-18 16:18:58 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-18 16:18:58 +0000 |
| commit | 776b85ba457ff82f795c6c65b5574ef27e611097 (patch) | |
| tree | ba3ddce3ac37c4edb8e3105390e4de959eba3ca9 /src/cpu | |
| parent | a41b939294c2e90197c57a2faa565bf48d4b506d (diff) | |
| download | coreboot-776b85ba457ff82f795c6c65b5574ef27e611097.tar.xz | |
Remove fallback/normal handling in mainboards'
romstage.c like r5255 did for failover/fallback/normal
mainboards.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram_disable.c | 24 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram_disable.c | 24 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram_disable.c | 24 |
3 files changed, 0 insertions, 72 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c index 939ec42aaf..4d108765c5 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram_disable.c +++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c @@ -25,30 +25,6 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; -#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist); /* No servicable parts below this line .. */ diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c index 6dac367c4d..cbf7cdd37b 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c @@ -27,30 +27,6 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; -#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist); /* No servicable parts below this line .. */ diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c index 9af667d655..32d921e7d6 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6fx/cache_as_ram_disable.c @@ -27,30 +27,6 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; -#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist); /* No servicable parts below this line .. */ |