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authorGreg Watson <jarrah@users.sourceforge.net>2004-03-07 22:24:05 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-03-07 22:24:05 +0000
commita3d26484cc98bc24a7d375a45637671dc6b67585 (patch)
tree4387c6a538d0dd4198013e4758a200b503dfc5b2 /src/cpu
parentefa1f324afd56dae5c6917dd1715a3efaf3886e3 (diff)
downloadcoreboot-a3d26484cc98bc24a7d375a45637671dc6b67585.tar.xz
*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/ppc/ppc7xx/Config.lb4
-rw-r--r--src/cpu/ppc/ppc7xx/cache.S23
-rw-r--r--src/cpu/ppc/ppc7xx/clock.c27
-rw-r--r--src/cpu/ppc/ppc7xx/ppc7xx.inc35
4 files changed, 58 insertions, 31 deletions
diff --git a/src/cpu/ppc/ppc7xx/Config.lb b/src/cpu/ppc/ppc7xx/Config.lb
index 2f77272957..ec606552f1 100644
--- a/src/cpu/ppc/ppc7xx/Config.lb
+++ b/src/cpu/ppc/ppc7xx/Config.lb
@@ -17,3 +17,7 @@ default DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc
+object clock.o
+object cache.S
+initobject clock.o
+initobject cache.S
diff --git a/src/cpu/ppc/ppc7xx/cache.S b/src/cpu/ppc/ppc7xx/cache.S
new file mode 100644
index 0000000000..237b178bdf
--- /dev/null
+++ b/src/cpu/ppc/ppc7xx/cache.S
@@ -0,0 +1,23 @@
+#define ASM
+#include "ppcreg.h"
+#include <ppc_asm.tmpl>
+
+#define NUM_CACHE_LINES 128*8
+#define L1_CACHE_LINE_SIZE 32
+#define cache_flush_buffer 0x1000
+
+/*
+ * Flush data cache
+ * Do this by just reading lots of stuff into the cache.
+ */
+.globl flush_dcache
+flush_dcache:
+ lis r3,cache_flush_buffer@h
+ ori r3,r3,cache_flush_buffer@l
+ li r4,NUM_CACHE_LINES
+ mtctr r4
+0: lwz r4,0(r3)
+ addi r3,r3,L1_CACHE_LINE_SIZE
+ bdnz 0b
+ blr
+
diff --git a/src/cpu/ppc/ppc7xx/clock.c b/src/cpu/ppc/ppc7xx/clock.c
new file mode 100644
index 0000000000..b14f7c6f57
--- /dev/null
+++ b/src/cpu/ppc/ppc7xx/clock.c
@@ -0,0 +1,27 @@
+#include <ppc.h>
+
+static int PLL_multiplier[] = {
+ 25, /* 0000 - 2.5x */
+ 75, /* 0001 - 7.5x */
+ 70, /* 0010 - 7x */
+ 10, /* 0011 - bypass */
+ 20, /* 0100 - 2x */
+ 65, /* 0101 - 6.5x */
+ 100, /* 0110 - 10x */
+ 45, /* 0111 - 4.5x */
+ 30, /* 1000 - 3x */
+ 55, /* 1001 - 5.5x */
+ 40, /* 1010 - 4x */
+ 50, /* 1011 - 5x */
+ 80, /* 1100 - 8x */
+ 60, /* 1101 - 6x */
+ 35, /* 1110 - 3.5x */
+ 0, /* 1111 - off */
+};
+
+unsigned long
+get_clock_speed(void)
+{
+ unsigned long clock = CONFIG_SYS_CLK_FREQ * 1000000;
+ return clock * PLL_multiplier[ppc_gethid1() >> 28] / 10;
+}
diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc
index 3391b28a44..c82ab2f370 100644
--- a/src/cpu/ppc/ppc7xx/ppc7xx.inc
+++ b/src/cpu/ppc/ppc7xx/ppc7xx.inc
@@ -56,37 +56,10 @@
/*
* Clear segment registers (LinuxBIOS doesn't use these)
*/
- mtsr 0, r0
- isync
- mtsr 1, r0
- isync
- mtsr 2, r0
- isync
- mtsr 3, r0
- isync
- mtsr 4, r0
- isync
- mtsr 5, r0
- isync
- mtsr 6, r0
- isync
- mtsr 7, r0
- isync
- mtsr 8, r0
- isync
- mtsr 9, r0
- isync
- mtsr 10, r0
- isync
- mtsr 11, r0
- isync
- mtsr 12, r0
- isync
- mtsr 13, r0
- isync
- mtsr 14, r0
- isync
- mtsr 15, r0
+ li r3, 15
+1: mtsrin r3, r0
+ subic. r3, r3, 1
+ bge 1b
isync
/*