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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-06-20 14:38:53 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-24 10:13:06 +0200 |
| commit | b38e0c3509d15d2be88bf194b637064bb1e80075 (patch) | |
| tree | 3b643ec8885fff79d3398814553205b9ecc560b0 /src/cpu | |
| parent | 52e61183cc98d132754970112592e0ebe1605d42 (diff) | |
| download | coreboot-b38e0c3509d15d2be88bf194b637064bb1e80075.tar.xz | |
Properly identify ACPI C3 states in _CST table.
Dump and disassemble ACPI tables and look in _CST.
In the last entry the state was getting set to 0:
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000030, // Address
0x01, // Access Size
)
},
0x00000000, // State
0x0000005A, // Latency
0x000000C8 // Power
}
Now it is properly identifed as state 3:
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000030, // Address
0x01, // Access Size
)
},
0x00000003, // State
0x0000005A, // Latency
0x000000C8 // Power
}
Change-Id: Ie0a68606c5a43ac5fb5ba7bb9a3fef933ad67b64
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1297
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_206ax/acpi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index dea23e7774..5d3f3a02bb 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -79,7 +79,7 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, length += acpigen_write_CST_package_entry(&cstates[c2]); } if (c3 > 0) { - cstates[c2].ctype = 2; + cstates[c3].ctype = 3; length += acpigen_write_CST_package_entry(&cstates[c3]); } |